static int command_spixfer(int argc, char **argv)
{
int dev_id;
uint8_t offset;
int v = 0;
uint8_t data[32];
char *e;
int rv = 0;
if (argc != 5)
return EC_ERROR_PARAM_COUNT;
dev_id = strtoi(argv[2], &e, 0);
if (*e)
return EC_ERROR_PARAM2;
offset = strtoi(argv[3], &e, 0);
if (*e)
return EC_ERROR_PARAM3;
v = strtoi(argv[4], &e, 0);
if (*e)
return EC_ERROR_PARAM4;
if (strcasecmp(argv[1], "rlen") == 0) {
uint8_t cmd = 0x80 | offset;
/* Arbitrary length read; param4 = len */
if (v < 0 || v > sizeof(data))
return EC_ERROR_PARAM4;
rv = spi_transaction(&spi_devices[dev_id], &cmd, 1, data, v);
if (!rv)
ccprintf("Data: %.*h\n", v, data);
} else if (strcasecmp(argv[1], "w") == 0) {
/* 8-bit write */
uint8_t cmd[2] = { offset, v };
rv = spi_transaction(&spi_devices[dev_id], cmd, 2, NULL, 0);
/*
* Some SPI device needs a delay before accepting other
* commands, otherwise the write might be ignored.
*/
msleep(1);
} else {
return EC_ERROR_PARAM1;
}
return rv;
}
void write_phy(uint8_t reg, uint16_t data)
{
switch_bank(2);
spi_transaction(WRITE_CONTROL_REGISTER, MIREGADR, reg);
spi_transaction(WRITE_CONTROL_REGISTER, MIWRL, data & 0xFF);
spi_transaction(WRITE_CONTROL_REGISTER, MIWRH, (data>>8) & 0xFF);
switch_bank(3);
uint8_t read;
do {
read = spi_transaction(READ_CONTROL_REGISTER, MISTAT, 0);
} while(read & (1<<BUSY));
}
void read_signature(void) {
if (CRC_EOP != getch()) {
ram.isp.error++;
sendCDCbyte(STK_NOSYNC);
return;
}
sendCDCbyte(STK_INSYNC);
uint8_t high = spi_transaction(0x30, 0x00, 0x00, 0x00);
sendCDCbyte(high);
uint8_t middle = spi_transaction(0x30, 0x00, 0x01, 0x00);
sendCDCbyte(middle);
uint8_t low = spi_transaction(0x30, 0x00, 0x02, 0x00);
sendCDCbyte(low);
sendCDCbyte(STK_OK);
}
void universal(void) {
uint8_t ch;
fill(4);
ch = spi_transaction(ram.RingBuffer_Data[0], ram.RingBuffer_Data[1], ram.RingBuffer_Data[2], ram.RingBuffer_Data[3]);
breply(ch);
}
void trans_read_register(uint8_t address, uint8_t * buffer, uint8_t length){
/*
This function initiates a SPI transaction for reading
a register(s) in the transceiver block. It is assumed that
the SPI0 module is in 8-bit mode.
*/
/* We need to send arbitrary values after the address byte
because the transceiver autoincrements the address */
uint8_t write_data[length + 1];
write_data[0] = address;
//memset(write_data + 1, 0x0, length);
for (int i = 1; i < length + 1; i++){
write_data[i] = 0x0;
}
uint8_t recv[length + 1];
spi_transaction(&SPI0, length + 1, write_data, recv);
/* Copy the received data back into the user's buffer */
//memcpy(buffer, recv + 1, length);
for (int i = 0; i < length + 1; i++){
if(i > 0){
buffer[i-1] = recv[i];
}
}
}
void ESP8266AVRISP::universal() {
int w;
uint8_t ch;
fill(4);
ch = spi_transaction(buff[0], buff[1], buff[2], buff[3]);
breply(ch);
}
/**
****************************************************************************************
* @brief Issue a command to Erase a given address
*
* @param[in] address: Address that belongs to the block64/block32/sector range
* @param[in] spiEraseModule: BLOCK_ERASE_64, BLOCK_ERASE_32, SECTOR_ERASE
* @return error code or success (ERR_OK)
****************************************************************************************
*/
int8_t spi_flash_block_erase(uint32_t address, SPI_erase_module_t spiEraseModule)
{
if (spi_flash_set_write_enable() != ERR_OK) // send [Write Enable] instruction
return ERR_TIMEOUT;
spi_set_bitmode(SPI_MODE_32BIT);
spi_transaction( (spiEraseModule<<24) | address); // Command for erasing a sector
return spi_flash_wait_till_ready();
}
static void ICACHE_FLASH_ATTR enc_setbits_reg( u8 reg, u8 bits )
{
// no automatic bank switching in this function !!!
u8 addr = reg & ENC_REG_ADDR_MASK;
enc_select();
spi_transaction(SPI_USED, 8, (ENC_SPI_OP_BFS | addr), 0, 0, 8, bits, 0, 0);
enc_deselect();
}
/**
****************************************************************************************
* @brief Write Status Register
* @param[in] dataToWrite: Value to be written to Status Register
* @return error code or success (ERR_OK)
****************************************************************************************
*/
int32_t spi_flash_write_status_reg(uint8_t dataToWrite)
{
int8_t spi_flash_status;
spi_flash_status = spi_flash_wait_till_ready();
if (spi_flash_status != ERR_OK)
return spi_flash_status; // an error has occured
spi_set_bitmode(SPI_MODE_16BIT);
spi_transaction((WRITE_STATUS_REG<<8) | dataToWrite); // send Write Status Register-1 instruction
return spi_flash_wait_till_ready();
}
uint32 Farmy::check(int channel) {
uint8 cmd = (0b11 << 3) | channel;
const uint32 COMMAND_LENGTH = 5;
const uint32 RESPONSE_LENGTH = 12;
uint32 retval = spi_transaction(HSPI, 0, 0, 0, 0, COMMAND_LENGTH, cmd, RESPONSE_LENGTH, 0);
retval = retval & 0x3FF; // mask to 10-bit value
return retval;
}
void usb_spi_deferred(struct usb_spi_config const *config)
{
uint16_t count;
uint8_t write_count;
uint8_t read_count;
uint16_t res;
/*
* If our overall enabled state has changed we call the board specific
* enable or disable routines and save our new state.
*/
int enabled = (config->state->enabled_host &
config->state->enabled_device);
if (enabled ^ config->state->enabled) {
if (enabled)
usb_spi_board_enable(config);
else
usb_spi_board_disable(config);
config->state->enabled = enabled;
}
/*
* And if there is a USB packet waiting we process it and generate a
* response.
*/
count = usb_spi_read_packet(config);
write_count = config->buffer[0];
read_count = config->buffer[1];
if (!count || (!read_count && !write_count))
return;
if (!config->state->enabled) {
res = USB_SPI_DISABLED;
} else if (write_count > USB_SPI_MAX_WRITE_COUNT ||
write_count != (count - HEADER_SIZE)) {
res = USB_SPI_WRITE_COUNT_INVALID;
} else if (read_count > USB_SPI_MAX_READ_COUNT) {
res = USB_SPI_READ_COUNT_INVALID;
} else {
res = usb_spi_map_error(
spi_transaction(SPI_FLASH_DEVICE,
config->buffer + HEADER_SIZE,
write_count,
config->buffer + HEADER_SIZE,
read_count));
}
memcpy(config->buffer, &res, HEADER_SIZE);
usb_spi_write_packet(config, read_count + HEADER_SIZE);
}
STATIC void machine_hspi_transfer(mp_obj_base_t *self_in, size_t len, const uint8_t *src, uint8_t *dest) {
(void)self_in;
if (dest == NULL) {
// fast case when we only need to write data
size_t chunk_size = 1024;
size_t count = len / chunk_size;
size_t i = 0;
for (size_t j = 0; j < count; ++j) {
for (size_t k = 0; k < chunk_size; ++k) {
spi_tx8fast(HSPI, src[i]);
++i;
}
ets_loop_iter();
}
while (i < len) {
spi_tx8fast(HSPI, src[i]);
++i;
}
} else {
// we need to read and write data
// Process data in chunks, let the pending tasks run in between
size_t chunk_size = 1024; // TODO this should depend on baudrate
size_t count = len / chunk_size;
size_t i = 0;
for (size_t j = 0; j < count; ++j) {
for (size_t k = 0; k < chunk_size; ++k) {
dest[i] = spi_transaction(HSPI, 0, 0, 0, 0, 8, src[i], 8, 0);
++i;
}
ets_loop_iter();
}
while (i < len) {
dest[i] = spi_transaction(HSPI, 0, 0, 0, 0, 8, src[i], 8, 0);
++i;
}
}
}
/**
****************************************************************************************
* @brief Erase chip
* @note In order for the erasure to succeed, all locking options must be disabled.
* @return error code or success (ERR_OK)
****************************************************************************************
*/
int8_t spi_flash_chip_erase(void)
{
uint8_t status;
if (spi_flash_set_write_enable() != ERR_OK) // send [Write Enable] instruction
return ERR_TIMEOUT;
spi_set_bitmode(SPI_MODE_8BIT);
spi_transaction(CHIP_ERASE); // Command for Chip Erase
status = spi_flash_wait_till_ready();
return status;
}
/**
****************************************************************************************
* @brief Sends the Power-Down instruction
* Remark: The function spi_flash_release_from_powerdown() is used to enable the IC again
* The power-down state will be entered tDP (3uS for W25X10CL) after CS is returned to high.
****************************************************************************************
*/
int32_t spi_flash_power_down(void)
{
int8_t spi_flash_status;
spi_flash_status = spi_flash_wait_till_ready();
if (spi_flash_status != ERR_OK)
return spi_flash_status; // an error has occured
spi_set_bitmode(SPI_MODE_8BIT);
spi_transaction(POWER_DOWN); // SPI transaction to Power-down the SPI Flash IC
return ERR_OK;
}
void start_pmode() {
spi_init();
// following delays may not work on all targets...
pinMode(RESET, OUTPUT);
digitalWrite(RESET, HIGH);
pinMode(SCK, OUTPUT);
digitalWrite(SCK, LOW);
delay(50);
digitalWrite(RESET, LOW);
delay(50);
pinMode(MISO, INPUT);
pinMode(MOSI, OUTPUT);
spi_transaction(0xAC, 0x53, 0x00, 0x00);
pmode = 1;
}
void ESP8266AVRISP::start_pmode() {
SPI.begin();
SPI.setFrequency(_spi_freq);
SPI.setHwCs(false);
// try to sync the bus
SPI.transfer(0x00);
digitalWrite(_reset_pin, _resetLevel(false));
delayMicroseconds(50);
digitalWrite(_reset_pin, _resetLevel(true));
delay(30);
spi_transaction(0xAC, 0x53, 0x00, 0x00);
pmode = 1;
}
void set_mac(uint8_t mac[6])
{
switch_bank(3);
spi_transaction(WRITE_CONTROL_REGISTER, MAADR1, mac[0]);
spi_transaction(WRITE_CONTROL_REGISTER, MAADR2, mac[1]);
spi_transaction(WRITE_CONTROL_REGISTER, MAADR3, mac[2]);
spi_transaction(WRITE_CONTROL_REGISTER, MAADR4, mac[3]);
spi_transaction(WRITE_CONTROL_REGISTER, MAADR5, mac[4]);
spi_transaction(WRITE_CONTROL_REGISTER, MAADR6, mac[5]);
}
static int printrx(const char *desc, const uint8_t *txdata, int txlen,
int rxlen)
{
uint8_t rxdata[32];
int rv;
int i;
rv = spi_transaction(SPI_FLASH_DEVICE, txdata, txlen, rxdata, rxlen);
if (rv)
return rv;
CPRINTS("%-12s:", desc);
for (i = 0; i < rxlen; i++)
CPRINTS(" 0x%02x", rxdata[i]);
CPUTS("\n");
return EC_SUCCESS;
}
/**
****************************************************************************************
* @brief Issue a Write Disable Command
* @return error code or success (ERR_OK)
****************************************************************************************
*/
int8_t spi_flash_set_write_disable(void)
{
uint32_t commandSendCount;
uint32_t statusReadCount;
uint8_t status;
if (spi_flash_wait_till_ready() == ERR_OK)
{
spi_set_bitmode(SPI_MODE_8BIT); // set SPI bitmode to 8-bit
for (commandSendCount = 0; commandSendCount < MAX_COMMAND_SEND_COUNT; commandSendCount++)
{
spi_transaction(WRITE_DISABLE); // send instruction
for (statusReadCount = 0; statusReadCount < MAX_READY_WAIT_COUNT; statusReadCount++)
{
status = spi_flash_read_status_reg();
if ( ((status & STATUS_BUSY) == 0) && ((status & STATUS_WEL) == 0) )
return ERR_OK;
}
}
}
return ERR_TIMEOUT;
}
void start_pmode(void) {
// set hardware SS to output so we can use SPI master mode
AVR_SPI_DDR |= (1 << AVR_HARDWARE_SS);
AVR_SPI_PORT |= (1 << AVR_HARDWARE_SS);
spi_init();
// following delays may not work on all targets...
AVR_SPI_DDR |= (1 << AVR_SS); // OUTPUT
AVR_SPI_PORT |= (1 << AVR_SS); // HIGH
AVR_SPI_DDR |= (1 << AVR_SCK); // OUTPUT
AVR_SPI_PORT &= ~(1 << AVR_SCK); // LOW
_delay_ms(50 + EXTRA_SPI_DELAY);
AVR_SPI_PORT &= ~(1 << AVR_SS); // LOW
_delay_ms(50 + EXTRA_SPI_DELAY); // extra delay added from adafruit <--
AVR_SPI_DDR &= ~(1 << AVR_MISO); // INPUT
AVR_SPI_DDR |= (1 << AVR_MOSI); // OUTPUT
spi_transaction(0xAC, 0x53, 0x00, 0x00);
// set pmode flag, do NOT reset other ISP values here!
ram.isp.pmode = true;
// clear all pending HID reports
clearHIDReports();
// do not write Serial stuff into buffer, we need this ram now
LRingBuffer_DisableBuffer(&ram.RingBuffer);
// reset LEDs
ram.PulseMSRemaining.whole = 0;
LEDs_SetAllLEDs(LEDS_NO_LEDS);
return;
}
/**
****************************************************************************************
* @brief Read Status Register
* @return Status Register value
****************************************************************************************
*/
uint8_t spi_flash_read_status_reg(void)
{
//no 'add spi_flash_wait_till_ready()' here
spi_set_bitmode(SPI_MODE_16BIT); // set SPI bitmode to 16-bit
return spi_transaction((uint16_t)(READ_STATUS_REG<<8));
}
/**
****************************************************************************************
* @brief Sends the Release from Power-Down instruction
* Remark: This function is used to restore the IC from power-down mode
* You must ensure that the CS line will stay high after this instruction is sent for
* at least tRES1 DP (3uS for W25X10CL).
****************************************************************************************
*/
int32_t spi_flash_release_from_power_down(void)
{
spi_set_bitmode(SPI_MODE_8BIT);
spi_transaction(REL_POWER_DOWN); // SPI transaction to Power-down the SPI Flash IC
return ERR_OK;
}
void transmit_data(uint8_t * data, size_t len)
{
switch_bank(0);
spi_transaction(WRITE_CONTROL_REGISTER, ETXSTL, 0x00);
spi_transaction(WRITE_CONTROL_REGISTER, ETXSTH, 0x10);
spi_transaction(WRITE_CONTROL_REGISTER, EWRPTL, 0x00);
spi_transaction(WRITE_CONTROL_REGISTER, EWRPTH, 0x10);
spi_transaction(WRITE_BUFFER_MEMORY, 0x1A, 0b00000000); //control byte
for(size_t i = 0; i < len; i++) {
spi_transaction(WRITE_BUFFER_MEMORY, 0x1A, data[i]);
}
uint16_t end = 0x1000 + len;
spi_transaction(WRITE_CONTROL_REGISTER, ETXNDL, end & 0xFF);
spi_transaction(WRITE_CONTROL_REGISTER, ETXNDH, (end>>8) & 0xFF);
spi_transaction(BIT_FIELD_SET, ECON1, (1<<TXRTS));
uint8_t reg;
do {
reg = spi_transaction(READ_CONTROL_REGISTER, ECON1, 0);
} while(reg & (1<<TXRTS));
reg = spi_transaction(READ_CONTROL_REGISTER, ESTAT, 0);
if(reg & (1<<TXABRT)) {
puts("Error occured during transmission");
}
if(reg & (1<<LATECOL)) {
puts("Late collision occured");
}
spi_transaction(WRITE_CONTROL_REGISTER, ERDPTL, (end+1) & 0xFF);
spi_transaction(WRITE_CONTROL_REGISTER, ERDPTH, ((end+1)>>8) & 0xFF);
for(int i = 0; i < 7; i++) {
printf("0x%02X ", spi_transaction(READ_BUFFER_MEMORY, 0x1A, 0));
}
puts("");
//}
}
void ethernet_initialize(uint8_t mac[6])
{
//Conf the LEDs
write_phy(PHLCON, 0b0011110000010011);
//Configure some buffers and MAC stuff for half duplex
//Recieve buffer spans 0x0000 to 0x0FFF
switch_bank(0);
spi_transaction(WRITE_CONTROL_REGISTER, ERXSTL, 0x00);
spi_transaction(WRITE_CONTROL_REGISTER, ERXSTH, 0x00);
spi_transaction(WRITE_CONTROL_REGISTER, ERXNDL, 0xFF);
spi_transaction(WRITE_CONTROL_REGISTER, ERXNDH, 0x0F);
spi_transaction(WRITE_CONTROL_REGISTER, ERXRDPTL, 0x00);
spi_transaction(WRITE_CONTROL_REGISTER, ERXRDPTH, 0x00);
//Transmit buffers covers 0x1000 to 0x1FFF
//...
uint8_t reg;
do {
reg = spi_transaction(READ_CONTROL_REGISTER, ESTAT, 0);
} while(!(reg & (1<<CLKRDY)));
//MAC settings
switch_bank(2);
spi_transaction(WRITE_CONTROL_REGISTER, MACON1, (1<<MARXEN));
spi_transaction(WRITE_CONTROL_REGISTER, MACON3, 0b11110000);
spi_transaction(WRITE_CONTROL_REGISTER, MACON4, 0b01000000); //DEFER
//1518 bytes
spi_transaction(WRITE_CONTROL_REGISTER, MAMXFLL, 0xEE);
spi_transaction(WRITE_CONTROL_REGISTER, MAMXFLH, 0x05);
spi_transaction(WRITE_CONTROL_REGISTER, MABBIPG, 0x12);
spi_transaction(WRITE_CONTROL_REGISTER, MAIPGL, 0x12);
spi_transaction(WRITE_CONTROL_REGISTER, MAIPGH, 0x0C);
set_mac(mac);
write_phy(PHCON2, (1<<HDLDIS));
write_phy(PHCON1, 0);
//Enable reception
spi_transaction(BIT_FIELD_SET, ECON1, (1<<RXEN));
puts("Enabled reception");
}
static void switch_bank(int bank)
{
spi_transaction(BIT_FIELD_CLEAR, ECON1, 0x3);
spi_transaction(BIT_FIELD_SET, ECON1, bank & 0x3);
}
int packets_available()
{
//Read EPKTCNT
switch_bank(1);
return(spi_transaction(READ_CONTROL_REGISTER, EPKTCNT, 0));
}
