static void cmd_bfc(enc28j60_t *dev, uint8_t reg, int8_t bank, uint8_t mask)
{
switch_bank(dev, bank);
gpio_clear(dev->cs_pin);
spi_transfer_reg(dev->spi, CMD_BFC | reg, mask, 0);
gpio_set(dev->cs_pin);
}
static int nvram_spi_read_9bit_addr(nvram_t *dev, uint8_t *dst, uint32_t src, size_t len)
{
nvram_spi_params_t *spi_dev = (nvram_spi_params_t *) dev->extra;
int status;
uint8_t cmd;
uint8_t addr;
cmd = NVRAM_SPI_CMD_READ;
/* The upper address bit is mixed into the command byte on certain devices,
* probably just to save a byte in the SPI transfer protocol. */
if (src > 0xff) {
cmd |= 0x08;
}
/* LSB of address */
addr = (src & 0xff);
spi_acquire(spi_dev->spi);
gpio_clear(spi_dev->cs);
/* Write command and address */
status = spi_transfer_reg(spi_dev->spi, (char)cmd, addr, NULL);
if (status < 0)
{
return status;
}
/* Keep holding CS and read data */
status = spi_transfer_bytes(spi_dev->spi, NULL, (char *)dst, len);
if (status < 0)
{
return status;
}
gpio_set(spi_dev->cs);
spi_release(spi_dev->spi);
/* status contains the number of bytes actually read from the SPI bus. */
return status;
}
static void cmd_wcr(enc28j60_t *dev, uint8_t reg, int8_t bank, uint8_t value)
{
switch_bank(dev, bank);
gpio_clear(dev->cs_pin);
spi_transfer_reg(dev->spi, CMD_WCR | reg, (char)value, 0);
gpio_set(dev->cs_pin);
}
void kw2xrf_write_dreg(uint8_t addr, uint8_t value)
{
kw2xrf_spi_transfer_head();
spi_transfer_reg(kw2xrf_spi, addr, value, NULL);
kw2xrf_spi_transfer_tail();
return;
}
uint8_t cc110x_get_reg_robust(cc110x_t *dev, uint8_t addr)
{
char result, result2;
unsigned int cpsr;
spi_acquire(dev->params.spi);
cpsr = disableIRQ();
cc110x_cs(dev);
do {
spi_transfer_reg(dev->params.spi, addr | CC110X_READ_BURST, CC110X_NOBYTE, &result);
spi_transfer_reg(dev->params.spi, addr | CC110X_READ_BURST, CC110X_NOBYTE, &result2);
} while (result != result2);
gpio_set(dev->params.cs);
restoreIRQ(cpsr);
spi_release(dev->params.spi);
return (uint8_t) result;
}
static void switch_bank(enc28j60_t *dev, int8_t bank)
{
/* only switch bank if needed */
if ((bank < 0) || (dev->bank == bank)) {
return;
}
/* clear old value */
gpio_clear(dev->cs_pin);
spi_transfer_reg(dev->spi, CMD_BFC | REG_ECON1, 0x03, 0);
gpio_set(dev->cs_pin);
/* set new value */
gpio_clear(dev->cs_pin);
spi_transfer_reg(dev->spi, CMD_BFS | REG_ECON1, bank, 0);
gpio_set(dev->cs_pin);
/* remember active bank */
dev->bank = bank;
}
uint8_t kw2xrf_read_dreg(uint8_t addr)
{
uint8_t value;
kw2xrf_spi_transfer_head();
spi_transfer_reg(kw2xrf_spi, (addr | MKW2XDRF_REG_READ),
0x0, (char *)&value);
kw2xrf_spi_transfer_tail();
return value;
}
static uint8_t cmd_rcr(enc28j60_t *dev, uint8_t reg, int8_t bank)
{
char res;
switch_bank(dev, bank);
gpio_clear(dev->cs_pin);
spi_transfer_reg(dev->spi, CMD_RCR | reg, 0, &res);
gpio_set(dev->cs_pin);
return (uint8_t)res;
}
void cc110x_write_reg(uint8_t addr, uint8_t value)
{
unsigned int cpsr;
spi_acquire(CC110X_SPI);
cpsr = disableIRQ();
cc110x_cs();
spi_transfer_reg(CC110X_SPI, addr, value, 0);
gpio_set(CC110X_CS);
restoreIRQ(cpsr);
spi_release(CC110X_SPI);
}
void cc110x_write_reg(cc110x_t *dev, uint8_t addr, uint8_t value)
{
unsigned int cpsr;
spi_acquire(dev->params.spi);
cpsr = disableIRQ();
cc110x_cs(dev);
spi_transfer_reg(dev->params.spi, addr, value, 0);
gpio_set(dev->params.cs);
restoreIRQ(cpsr);
spi_release(dev->params.spi);
}
void at86rf2xx_reg_write(const at86rf2xx_t *dev,
const uint8_t addr,
const uint8_t value)
{
spi_acquire(dev->spi);
gpio_clear(dev->cs_pin);
spi_transfer_reg(dev->spi,
AT86RF2XX_ACCESS_REG | AT86RF2XX_ACCESS_WRITE | addr,
value, 0);
gpio_set(dev->cs_pin);
spi_release(dev->spi);
}
int nrf24l01p_write_reg(const nrf24l01p_t *dev, char reg, char write)
{
/* Acquire exclusive access to the bus. */
spi_acquire(dev->spi, dev->cs, SPI_MODE, SPI_CLK);
spi_transfer_reg(dev->spi, dev->cs,
(CMD_W_REGISTER | (REGISTER_MASK & reg)), (uint8_t)write);
/* Release the bus for other threads. */
spi_release(dev->spi);
xtimer_spin(DELAY_AFTER_FUNC_TICKS);
return 0;
}
int nrf24l01p_read_reg(const nrf24l01p_t *dev, char reg, char *answer)
{
/* Acquire exclusive access to the bus. */
spi_acquire(dev->spi, dev->cs, SPI_MODE, SPI_CLK);
*answer = (char)spi_transfer_reg(dev->spi, dev->cs,
(CMD_R_REGISTER | (REGISTER_MASK & reg)),
CMD_NOP);
/* Release the bus for other threads. */
spi_release(dev->spi);
xtimer_spin(DELAY_AFTER_FUNC_TICKS);
return 0;
}
uint8_t cc110x_read_status(uint8_t addr)
{
char result;
unsigned int cpsr;
spi_acquire(CC110X_SPI);
cpsr = disableIRQ();
cc110x_cs();
spi_transfer_reg(CC110X_SPI, addr | CC1100_READ_BURST, CC1100_NOBYTE, &result);
gpio_set(CC110X_CS);
restoreIRQ(cpsr);
spi_release(CC110X_SPI);
return (uint8_t) result;
}
uint8_t cc110x_read_status(cc110x_t *dev, uint8_t addr)
{
char result;
unsigned int cpsr;
spi_acquire(dev->params.spi);
cpsr = disableIRQ();
cc110x_cs(dev);
spi_transfer_reg(dev->params.spi, addr | CC110X_READ_BURST, CC110X_NOBYTE, &result);
gpio_set(dev->params.cs);
restoreIRQ(cpsr);
spi_release(dev->params.spi);
return (uint8_t) result;
}
void at86rf2xx_sram_write(const at86rf2xx_t *dev,
const uint8_t offset,
const uint8_t *data,
const size_t len)
{
spi_acquire(dev->spi);
gpio_clear(dev->cs_pin);
spi_transfer_reg(dev->spi,
AT86RF2XX_ACCESS_SRAM | AT86RF2XX_ACCESS_WRITE,
(char)offset, NULL);
spi_transfer_bytes(dev->spi, (char *)data, NULL, len);
gpio_set(dev->cs_pin);
spi_release(dev->spi);
}
uint8_t at86rf2xx_reg_read(const at86rf2xx_t *dev, const uint8_t addr)
{
char value;
spi_acquire(dev->spi);
gpio_clear(dev->cs_pin);
spi_transfer_reg(dev->spi,
AT86RF2XX_ACCESS_REG | AT86RF2XX_ACCESS_READ | addr,
0, &value);
gpio_set(dev->cs_pin);
spi_release(dev->spi);
return (uint8_t)value;
}
int nrf24l01p_read_reg(nrf24l01p_t *dev, char reg, char *answer)
{
int status;
/* Acquire exclusive access to the bus. */
spi_acquire(dev->spi);
gpio_clear(dev->cs);
xtimer_spin(DELAY_CS_TOGGLE_TICKS);
status = spi_transfer_reg(dev->spi, (CMD_R_REGISTER | (REGISTER_MASK & reg)), CMD_NOP, answer);
xtimer_spin(DELAY_CS_TOGGLE_TICKS);
gpio_set(dev->cs);
/* Release the bus for other threads. */
spi_release(dev->spi);
xtimer_spin(DELAY_AFTER_FUNC_TICKS);
return status;
}
int nrf24l01p_write_reg(nrf24l01p_t *dev, char reg, char write)
{
int status;
char reg_content;
/* Acquire exclusive access to the bus. */
spi_acquire(dev->spi);
gpio_clear(dev->cs);
hwtimer_spin(DELAY_CS_TOGGLE_TICKS);
status = spi_transfer_reg(dev->spi, (CMD_W_REGISTER | (REGISTER_MASK & reg)), write, ®_content);
hwtimer_spin(DELAY_CS_TOGGLE_TICKS);
gpio_set(dev->cs);
/* Release the bus for other threads. */
spi_release(dev->spi);
hwtimer_spin(DELAY_AFTER_FUNC_TICKS);
return status;
}
static int nvram_spi_write_9bit_addr(nvram_t *dev, uint8_t *src, uint32_t dst, size_t len)
{
nvram_spi_params_t *spi_dev = (nvram_spi_params_t *) dev->extra;
int status;
uint8_t cmd;
uint8_t addr;
cmd = NVRAM_SPI_CMD_WRITE;
/* The upper address bit is mixed into the command byte on certain devices,
* probably just to save a byte in the SPI transfer protocol. */
if (dst > 0xff) {
cmd |= 0x08;
}
/* LSB of address */
addr = (dst & 0xff);
spi_acquire(spi_dev->spi);
gpio_clear(spi_dev->cs);
/* Enable writes */
status = spi_transfer_byte(spi_dev->spi, NVRAM_SPI_CMD_WREN, NULL);
if (status < 0)
{
return status;
}
gpio_set(spi_dev->cs);
xtimer_spin(NVRAM_SPI_CS_TOGGLE_TICKS);
gpio_clear(spi_dev->cs);
/* Write command and address */
status = spi_transfer_reg(spi_dev->spi, cmd, addr, NULL);
if (status < 0)
{
return status;
}
/* Keep holding CS and write data */
status = spi_transfer_bytes(spi_dev->spi, (char *)src, NULL, len);
if (status < 0)
{
return status;
}
gpio_set(spi_dev->cs);
spi_release(spi_dev->spi);
/* status contains the number of bytes actually written to the SPI bus. */
return status;
}
/**
* @brief Write a value to an 8 bit register in the LIS3DH.
*
* @param[in] reg The target register.
* @param[in] value The value to write.
*
* @return 0 on success
* @return -1 on error
*/
static int lis3dh_write_reg(const lis3dh_t *dev, const lis3dh_reg_t reg, const uint8_t value)
{
/* Set WRITE SINGLE mode */
uint8_t addr = (reg & LIS3DH_SPI_ADDRESS_MASK) | LIS3DH_SPI_WRITE_MASK | LIS3DH_SPI_SINGLE_MASK;
/* Acquire exclusive access to the bus. */
spi_acquire(dev->spi);
/* Perform the transaction */
gpio_clear(dev->cs);
if (spi_transfer_reg(dev->spi, addr, value, NULL) < 0) {
/* Transfer error */
gpio_set(dev->cs);
/* Release the bus for other threads. */
spi_release(dev->spi);
return -1;
}
gpio_set(dev->cs);
/* Release the bus for other threads. */
spi_release(dev->spi);
return 0;
}
