void nrf_wr_config(uint8_t reg, uint8_t val)
{
nrf_CSN_lo;
spi_wr(reg);
spi_wr(val);
nrf_CSN_hi;
}
void nrf_tx_addr(uint32_t addr)
{
nrf_CSN_lo;
spi_wr(W_TX_ADDRESS);
spi_wr((uint8_t)(addr & 0xff));
spi_wr((uint8_t)((addr >> 8) & 0xff));
spi_wr((uint8_t)((addr >> 16) & 0xff));
spi_wr((uint8_t)((addr >> 24) & 0xff));
nrf_CSN_hi;
}
void nrf_tx_payload(uint8_t *data,uint8_t len)
{
nrf_CSN_lo;
spi_wr(W_TX_PAYLOAD);
spi_wr_buf(data,len);
nrf_CSN_hi;
}
uint8_t nrf_rd_config(uint8_t reg)
{
nrf_CSN_lo;
spi_wr(R_CONFIG|reg);
uint8_t value = spi_rd();
nrf_CSN_hi;
return value;
}
uint32_t nrf_rd_tx_addr(void)
{
uint32_t addr;
nrf_CSN_lo;
spi_wr(R_TX_ADDRESS);
spi_rd_buf((uint8_t *)&addr,4);
nrf_CSN_hi;
return addr;
}
/**
* Return the status byte of CC2500
* @return cc2500 status
*/
char hal_cc2500_status(void) {
char x;
hal_pin_out(&cc_spinCS, 0); // CS enabled
hal_cc2500_wakeup();
spi_write(TI_CCxxx0_SNOP); // Send address
x = spi_wr(0); // Read data
hal_pin_out(&cc_spinCS, 1); // CS disabled
return x;
}
/**
* Reads a single configuration register at address "addr" and returns the
* value read.
*
* @param addr
* @return
*/
char hal_cc2500_readReg(char addr) {
char x;
hal_pin_out(&cc_spinCS, 0); // CS enabled
hal_cc2500_wakeup(); // Wait for CCxxxx ready
spi_write(addr | TI_CCxxx0_READ_SINGLE); // Send address
x = spi_wr(0); // Read data
hal_pin_out(&cc_spinCS, 1); // CS disabled
return x;
}
/**
* Special read function for reading status registers. Reads status register
* at register "addr" and returns the value read.
*
* @param addr
* @return
*/
char hal_cc2500_readStatus(char addr) {
char x;
hal_pin_out(&cc_spinCS, 0); // CS enabled
hal_cc2500_wakeup();
spi_write(addr | TI_CCxxx0_READ_BURST); // Send address
x = spi_wr(0); // Read data
hal_pin_out(&cc_spinCS, 1); // CS disabled
return x;
}
/**
* Reads multiple configuration registers, the first register being at address
* "addr". Values read are deposited sequentially starting at address
* "buffer", until "count" registers have been read.
*
* @param addr
* @param buffer
* @param count
*/
void hal_cc2500_readBurstReg(char addr, char *buffer, char count) {
char i;
hal_pin_out(&cc_spinCS, 0); // CS enabled
hal_cc2500_wakeup();
spi_write(addr | TI_CCxxx0_READ_BURST); // Send add
for (i = 0; i < count ; i++) {
buffer[i] = spi_wr(0); // Store data from last data RX
}
hal_pin_out(&cc_spinCS, 1); // CS disabled
}
void nrf_send(uint8_t * value, uint8_t len)
// Sends a data package to the default address. Be sure to send the correct
// amount of bytes as configured as payload on the receiver.
{
while (PTX) {} // Wait until last paket is send
CE_LO;
PTX = 1; // Set to transmitter mode
// TX_POWERUP; // Power up
CSN_LO; // Pull down chip select
spi_wr( FLUSH_TX ); // Write cmd to flush tx fifo
CSN_HI; // Pull up chip select
CSN_LO; // Pull down chip select
spi_wr( W_TX_PAYLOAD ); // Write cmd to write payload
spi_wr_buf(value,len); // Write payload
CSN_HI; // Pull up chip select
CE_HI; // Start transmission
}
int sflash_platform_send_recv_byte( void* platform_peripheral, unsigned char MOSI_val, void* MISO_addr )
{
// int ret;
uint8_t *rcv_buf;
if(MISO_addr != 0x00000000)
rcv_buf = MISO_addr;
else
rcv_buf = (uint8_t *)&spi_flash_recv;
*rcv_buf = spi_wr(MOSI_val);
#ifdef SPIFLASHDEBUG
printf("SPI RW %x %d, %x\r\n", MOSI_val, 1, *rcv_buf);
#endif
return 0;
}
int sflash_platform_init( int peripheral_id, void** platform_peripheral_out )
{
uint8_t temp1, temp2;
uint32_t j;
spi_flash_init();
SPI_FLASH_CS_LOW;
temp1 = spi_wr(0x90);
temp1 = spi_wr(0x00);
temp1 = spi_wr(0x00);
temp1 = spi_wr(0x00);
temp1 = spi_wr(0x00);
temp2 = spi_wr(0x00);
SPI_FLASH_CS_HIGH;
for(j=0; j<5000; j++);
printf("Flash ID1 %x, %x, %x\r\n", temp1, temp2, j);
SPI_FLASH_CS_LOW;
temp1 = spi_wr(0x90);
temp1 = spi_wr(0x00);
temp1 = spi_wr(0x00);
temp1 = spi_wr(0x00);
temp1 = spi_wr(0x00);
temp2 = spi_wr(0x00);
SPI_FLASH_CS_HIGH;
for(j=0; j<5000; j++);
printf("Flash ID2 %x, %x. %x\r\n", temp1, temp2, j);
return 0;
}
