static int spic_transfer(const u8 *cmd, int n_cmd, u8 *buf, int n_buf, int flag)
{
int retval = -1;
//spic_init();
ra_dbg("cmd(%x): %x %x %x %x , buf:%x len:%x, flag:%s \n",
n_cmd, cmd[0], cmd[1], cmd[2], cmd[3],
(buf)? (*buf) : 0, n_buf,
(flag == SPIC_READ_BYTES)? "read" : "write");
#if defined(CONFIG_RALINK_VITESSE_SWITCH_CONNECT_SPI_CS1)||defined(CONFIG_RALINK_SLIC_CONNECT_SPI_CS1)
/* config ARB and set the low or high active correctly according to the device */
ra_outl(RT2880_SPI_ARB_REG, SPIARB_ARB_EN|(SPIARB_SPI1_ACTIVE_MODE<<1)| SPIARB_SPI0_ACTIVE_MODE);
#if defined(CONFIG_RALINK_SPI_CS1_HIGH_ACTIVE)
ra_and(RT2880_SPI1_CTL_REG, (~SPIARB_SPI1_ACTIVE_MODE));
#else
ra_or(RT2880_SPI1_CTL_REG, (~SPIARB_SPI1_ACTIVE_MODE)&0x01);
#endif
#endif
ra_outl(RT2880_SPICFG_REG, SPICFG_MSBFIRST | SPICFG_TXCLKEDGE_FALLING | CFG_CLK_DIV | SPICFG_SPICLKPOL );
// assert CS and we are already CLK normal high
ra_and(RT2880_SPICTL_REG, ~(SPICTL_SPIENA_HIGH));
// write command
for (retval = 0; retval < n_cmd; retval++) {
ra_outl(RT2880_SPIDATA_REG, cmd[retval]);
ra_or(RT2880_SPICTL_REG, SPICTL_STARTWR);
if (spic_busy_wait()) {
retval = -1;
goto end_trans;
}
}
// read / write data
if (flag & SPIC_READ_BYTES) {
for (retval = 0; retval < n_buf; retval++) {
ra_or(RT2880_SPICTL_REG, SPICTL_STARTRD);
if (spic_busy_wait())
goto end_trans;
buf[retval] = (u8) ra_inl(RT2880_SPIDATA_REG);
}
}
else if (flag & SPIC_WRITE_BYTES) {
for (retval = 0; retval < n_buf; retval++) {
ra_outl(RT2880_SPIDATA_REG, buf[retval]);
ra_or(RT2880_SPICTL_REG, SPICTL_STARTWR);
if (spic_busy_wait())
goto end_trans;
}
}
end_trans:
// de-assert CS and
ra_or (RT2880_SPICTL_REG, (SPICTL_SPIENA_HIGH));
return retval;
}
/*
* @cmd: command and address
* @n_cmd: size of command, in bytes
* @buf: buffer into which data will be read/written
* @n_buf: size of buffer, in bytes
* @flag: tag as READ/WRITE
*
* @return: if write_onlu, -1 means write fail, or return writing counter.
* @return: if read, -1 means read fail, or return reading counter.
*/
static int spic_transfer(const u8 *cmd, int n_cmd, u8 *buf, int n_buf, int flag)
{
int retval = -1;
/*
ra_dbg("cmd(%x): %x %x %x %x , buf:%x len:%x, flag:%s \n",
n_cmd, cmd[0], cmd[1], cmd[2], cmd[3],
(buf)? (*buf) : 0, n_buf,
(flag == SPIC_READ_BYTES)? "read" : "write");
*/
// assert CS and we are already CLK normal high
ra_and(RT2880_SPI0_CTL_REG, ~(SPICTL_SPIENA_HIGH));
// write command
for (retval = 0; retval < n_cmd; retval++) {
ra_outl(RT2880_SPI0_DATA_REG, cmd[retval]);
ra_or(RT2880_SPI0_CTL_REG, SPICTL_STARTWR);
if (spic_busy_wait()) {
retval = -1;
goto end_trans;
}
}
// read / write data
if (flag & SPIC_READ_BYTES) {
for (retval = 0; retval < n_buf; retval++) {
ra_or(RT2880_SPI0_CTL_REG, SPICTL_STARTRD);
#ifndef READ_BY_PAGE
if (n_cmd != 1 && (retval & 0xffff) == 0) {
printf(".");
}
#endif
if (spic_busy_wait()) {
printf("\n");
goto end_trans;
}
buf[retval] = (u8) ra_inl(RT2880_SPI0_DATA_REG);
}
}
else if (flag & SPIC_WRITE_BYTES) {
for (retval = 0; retval < n_buf; retval++) {
ra_outl(RT2880_SPI0_DATA_REG, buf[retval]);
ra_or(RT2880_SPI0_CTL_REG, SPICTL_STARTWR);
if (spic_busy_wait()) {
goto end_trans;
}
}
}
end_trans:
// de-assert CS and
ra_or (RT2880_SPI0_CTL_REG, (SPICTL_SPIENA_HIGH));
return retval;
}
