void
eap1371_set_dac_rate(struct eap_softc *sc, int rate, int which)
{
int dac = which == 1 ? ESRC_DAC1 : ESRC_DAC2;
int freq, r;
int s;
/* Whatever, it works, so I'll leave it :) */
if (rate > 48000)
rate = 48000;
if (rate < 4000)
rate = 4000;
freq = ((rate << 15) + 1500) / 3000;
s = splaudio();
eap1371_src_wait(sc);
r = EREAD4(sc, E1371_SRC) & (E1371_SRC_DISABLE |
E1371_SRC_DISP2 | E1371_SRC_DISP1 | E1371_SRC_DISREC);
r |= (which == 1) ? E1371_SRC_DISP1 : E1371_SRC_DISP2;
EWRITE4(sc, E1371_SRC, r);
r = eap1371_src_read(sc, dac + ESRC_IREGS) & 0x00ff;
eap1371_src_write(sc, dac + ESRC_IREGS, r | ((freq >> 5) & 0xfc00));
eap1371_src_write(sc, dac + ESRC_VFF, freq & 0x7fff);
r = EREAD4(sc, E1371_SRC) & (E1371_SRC_DISABLE |
E1371_SRC_DISP2 | E1371_SRC_DISP1 | E1371_SRC_DISREC);
r &= ~(which == 1 ? E1371_SRC_DISP1 : E1371_SRC_DISP2);
EWRITE4(sc, E1371_SRC, r);
splx(s);
}
static void
pxa2x0_i2s_dmac_iintr(struct dmac_xfer *dx, int status)
{
struct pxa2x0_i2s_softc *sc = dx->dx_cookie;
struct pxa2x0_i2s_dma *p = sc->sc_rxdma;
int s;
if (p == NULL) {
panic("pxa2x_i2s_dmac_iintr: bad RX DMA descriptor!");
}
if (p->dx != dx) {
panic("pxa2x_i2s_dmac_iintr: xfer mismatch!");
}
if (status) {
printf("%s: pxa2x0_i2s_dmac_iintr: "
"non-zero completion status %d\n",
sc->sc_dev.dv_xname, status);
}
s = splaudio();
(sc->sc_rxfunc)(sc->sc_rxarg);
splx(s);
}
static void
ad_write(struct ad1848_softc *sc, int reg, int data)
{
int s = splaudio();
ADWRITE(sc, AD1848_IADDR, (reg & 0xff) | sc->MCE_bit);
ADWRITE(sc, AD1848_IDATA, data & 0xff);
splx(s);
/* printf("(%02x->%02x) ", reg|sc->MCE_bit, data); */
}
static void
free_all_jacks(struct umidi_softc *sc)
{
int s;
s = splaudio();
if (sc->sc_out_jacks) {
free(sc->sc_jacks, M_USBDEV);
sc->sc_jacks = sc->sc_in_jacks = sc->sc_out_jacks = NULL;
}
splx(s);
}
static int
ad_read(struct ad1848_softc *sc, int reg)
{
int x, s;
s = splaudio();
ADWRITE(sc, AD1848_IADDR, (reg & 0xff) | sc->MCE_bit);
x = ADREAD(sc, AD1848_IDATA);
splx(s);
/* printf("(%02x<-%02x) ", reg|sc->MCE_bit, x); */
return x;
}
int
am7930_commit_settings(void *addr)
{
struct am7930_softc *sc = addr;
uint16_t ger, gr, gx, stgr;
uint8_t mmr2, mmr3;
int s, level;
DPRINTF(("sa_commit.\n"));
gx = gx_coeff[sc->sc_rlevel];
stgr = gx_coeff[sc->sc_mlevel];
level = (sc->sc_plevel * (256 + NGER)) >> 8;
if (level >= 256) {
ger = ger_coeff[level - 256];
gr = gx_coeff[255];
} else {
ger = ger_coeff[0];
gr = gx_coeff[level];
}
s = splaudio();
mmr2 = AM7930_IREAD(sc, AM7930_IREG_MAP_MMR2);
if (sc->sc_out_port == AUDIOAMD_SPEAKER_VOL)
mmr2 |= AM7930_MMR2_LS;
else
mmr2 &= ~AM7930_MMR2_LS;
AM7930_IWRITE(sc, AM7930_IREG_MAP_MMR2, mmr2);
mmr3 = AM7930_IREAD(sc, AM7930_IREG_MAP_MMR3);
if (sc->sc_mic_mute)
mmr3 |= AM7930_MMR3_MUTE;
else
mmr3 &= ~AM7930_MMR3_MUTE;
AM7930_IWRITE(sc, AM7930_IREG_MAP_MMR3, mmr3);
AM7930_IWRITE(sc, AM7930_IREG_MAP_MMR1,
AM7930_MMR1_GX | AM7930_MMR1_GER |
AM7930_MMR1_GR | AM7930_MMR1_STG);
AM7930_IWRITE16(sc, AM7930_IREG_MAP_GX, gx);
AM7930_IWRITE16(sc, AM7930_IREG_MAP_STG, stgr);
AM7930_IWRITE16(sc, AM7930_IREG_MAP_GR, gr);
AM7930_IWRITE16(sc, AM7930_IREG_MAP_GER, ger);
splx(s);
return 0;
}
int
pxa2x0_i2s_halt_input(void *hdl)
{
struct pxa2x0_i2s_softc *sc = hdl;
int s;
s = splaudio();
if (sc->sc_rxdma) {
pxa2x0_dmac_abort_xfer(sc->sc_rxdma->dx);
sc->sc_rxdma = NULL;
}
splx(s);
return 0;
}
void
eap1371_reset_codec(void *sc_)
{
struct eap_softc *sc = sc_;
u_int32_t icsc;
int s;
s = splaudio();
icsc = EREAD4(sc, EAP_ICSC);
EWRITE4(sc, EAP_ICSC, icsc | E1371_SYNC_RES);
delay(20);
EWRITE4(sc, EAP_ICSC, icsc & ~E1371_SYNC_RES);
delay(1);
splx(s);
return;
}
static __inline void
eap1371_ready_codec(struct eap_softc *sc, u_int8_t a, u_int32_t wd)
{
int to, s;
u_int32_t src, t;
for (to = 0; to < EAP_WRITE_TIMEOUT; to++) {
if (!(EREAD4(sc, E1371_CODEC) & E1371_CODEC_WIP))
break;
delay(1);
}
if (to == EAP_WRITE_TIMEOUT)
printf("%s: eap1371_ready_codec timeout 1\n",
sc->sc_dev.dv_xname);
s = splaudio();
src = eap1371_src_wait(sc) & E1371_SRC_CTLMASK;
EWRITE4(sc, E1371_SRC, src | E1371_SRC_STATE_OK);
for (to = 0; to < EAP_READ_TIMEOUT; to++) {
t = EREAD4(sc, E1371_SRC);
if ((t & E1371_SRC_STATE_MASK) == 0)
break;
delay(1);
}
if (to == EAP_READ_TIMEOUT)
printf("%s: eap1371_ready_codec timeout 2\n",
sc->sc_dev.dv_xname);
for (to = 0; to < EAP_READ_TIMEOUT; to++) {
t = EREAD4(sc, E1371_SRC);
if ((t & E1371_SRC_STATE_MASK) == E1371_SRC_STATE_OK)
break;
delay(1);
}
if (to == EAP_READ_TIMEOUT)
printf("%s: eap1371_ready_codec timeout 3\n",
sc->sc_dev.dv_xname);
EWRITE4(sc, E1371_CODEC, wd);
eap1371_src_wait(sc);
EWRITE4(sc, E1371_SRC, src);
splx(s);
}
void
eap1371_set_adc_rate(struct eap_softc *sc, int rate)
{
int freq, n, truncm;
int out;
int s;
/* Whatever, it works, so I'll leave it :) */
if (rate > 48000)
rate = 48000;
if (rate < 4000)
rate = 4000;
n = rate / 3000;
if ((1 << n) & SRC_MAGIC)
n--;
truncm = ((21 * n) - 1) | 1;
freq = ((48000 << 15) / rate) * n;
if (rate >= 24000) {
if (truncm > 239)
truncm = 239;
out = ESRC_SET_TRUNC((239 - truncm) / 2);
} else {
if (truncm > 119)
truncm = 119;
out = ESRC_SMF | ESRC_SET_TRUNC((119 - truncm) / 2);
}
out |= ESRC_SET_N(n);
s = splaudio();
eap1371_src_write(sc, ESRC_ADC+ESRC_TRUNC_N, out);
out = eap1371_src_read(sc, ESRC_ADC+ESRC_IREGS) & 0xff;
eap1371_src_write(sc, ESRC_ADC+ESRC_IREGS, out |
ESRC_SET_VFI(freq >> 15));
eap1371_src_write(sc, ESRC_ADC+ESRC_VFF, freq & 0x7fff);
eap1371_src_write(sc, ESRC_ADC_VOLL, ESRC_SET_ADC_VOL(n));
eap1371_src_write(sc, ESRC_ADC_VOLR, ESRC_SET_ADC_VOL(n));
splx(s);
}
/*
* Lower-level routines
*/
int
ad1848_commit_settings(void *addr)
{
struct ad1848_softc *sc = addr;
int timeout;
u_char fs;
int s;
if (!sc->need_commit)
return 0;
s = splaudio();
ad1848_mute_monitor(sc, 1);
/* Enables changes to the format select reg */
ad_set_MCE(sc, 1);
fs = sc->speed_bits | sc->format_bits;
if (sc->channels == 2)
fs |= FMT_STEREO;
ad_write(sc, SP_CLOCK_DATA_FORMAT, fs);
/*
* If mode == 2 (CS4231), set I28 also. It's the capture format
* register.
*/
if (sc->mode == 2) {
/* Gravis Ultrasound MAX SDK sources says something about
* errata sheets, with the implication that these inb()s
* are necessary.
*/
(void)ADREAD(sc, AD1848_IDATA);
(void)ADREAD(sc, AD1848_IDATA);
/*
* Write to I8 starts resynchronization. Wait until it
* completes.
*/
timeout = AD1848_TIMO;
while (timeout > 0 && ADREAD(sc, AD1848_IADDR) == SP_IN_INIT)
timeout--;
ad_write(sc, CS_REC_FORMAT, fs);
/* Gravis Ultrasound MAX SDK sources says something about
* errata sheets, with the implication that these inb()s
* are necessary.
*/
(void)ADREAD(sc, AD1848_IDATA);
(void)ADREAD(sc, AD1848_IDATA);
/* Now wait for resync for capture side of the house */
}
/*
* Write to I8 starts resynchronization. Wait until it completes.
*/
timeout = AD1848_TIMO;
while (timeout > 0 && ADREAD(sc, AD1848_IADDR) == SP_IN_INIT)
timeout--;
if (ADREAD(sc, AD1848_IADDR) == SP_IN_INIT)
printf("ad1848_commit: Auto calibration timed out\n");
/*
* Starts the calibration process and enters playback mode after it.
*/
ad_set_MCE(sc, 0);
wait_for_calibration(sc);
ad1848_mute_monitor(sc, 0);
splx(s);
sc->need_commit = 0;
return 0;
}