/* get truncated string from database */
void sort_getstring_for_dirent(char *ptr, uint32_t addr) {
uint8_t leaf_offset;
if(addr & 0x80000000) {
/* is directory link, name offset 4 */
leaf_offset = sram_readbyte(addr + 4 + SRAM_MENU_ADDR);
sram_readblock(ptr, addr + 5 + leaf_offset + SRAM_MENU_ADDR, 20);
} else {
/* is file link, name offset 6 */
leaf_offset = sram_readbyte(addr + 6 + SRAM_MENU_ADDR);
sram_readblock(ptr, addr + 7 + leaf_offset + SRAM_MENU_ADDR, 20);
}
ptr[20]=0;
}
/*
* SD2SNES menu loop.
* monitors menu selection. return when selection was made.
*/
uint8_t menu_main_loop() {
uint8_t cmd = 0;
sram_writebyte(0, SRAM_CMD_ADDR);
while(!cmd) {
if(!get_snes_reset()) {
while(!sram_reliable())printf("hurr\n");
cmd = sram_readbyte(SRAM_CMD_ADDR);
}
if(get_snes_reset()) {
cmd = 0;
}
sleep_ms(20);
cli_entrycheck();
}
return cmd;
}
uint32_t load_spc(uint8_t* filename, uint32_t spc_data_addr, uint32_t spc_header_addr) {
DWORD filesize;
UINT bytes_read;
uint8_t data;
UINT j;
printf("%s\n", filename);
file_open(filename, FA_READ); /* Open SPC file */
if(file_res) return 0;
filesize = file_handle.fsize;
if (filesize < 65920) { /* At this point, we care about filesize only */
file_close(); /* since SNES decides if it is an SPC file */
sram_writebyte(0, spc_header_addr); /* If file is too small, destroy previous SPC header */
return 0;
}
set_mcu_addr(spc_data_addr);
f_lseek(&file_handle, 0x100L); /* Load 64K data segment */
for(;;) {
bytes_read = file_read();
if (file_res || !bytes_read) break;
FPGA_SELECT();
FPGA_TX_BYTE(0x98);
for(j=0; j<bytes_read; j++) {
FPGA_TX_BYTE(file_buf[j]);
FPGA_WAIT_RDY();
}
FPGA_DESELECT();
}
file_close();
file_open(filename, FA_READ); /* Reopen SPC file to reset file_getc state*/
set_mcu_addr(spc_header_addr);
f_lseek(&file_handle, 0x0L); /* Load 256 bytes header */
FPGA_SELECT();
FPGA_TX_BYTE(0x98);
for (j = 0; j < 256; j++) {
data = file_getc();
FPGA_TX_BYTE(data);
FPGA_WAIT_RDY();
}
FPGA_DESELECT();
file_close();
file_open(filename, FA_READ); /* Reopen SPC file to reset file_getc state*/
set_mcu_addr(spc_header_addr+0x100);
f_lseek(&file_handle, 0x10100L); /* Load 128 DSP registers */
FPGA_SELECT();
FPGA_TX_BYTE(0x98);
for (j = 0; j < 128; j++) {
data = file_getc();
FPGA_TX_BYTE(data);
FPGA_WAIT_RDY();
}
FPGA_DESELECT();
file_close(); /* Done ! */
/* clear echo buffer to avoid artifacts */
uint8_t esa = sram_readbyte(spc_header_addr+0x100+0x6d);
uint8_t edl = sram_readbyte(spc_header_addr+0x100+0x7d);
uint8_t flg = sram_readbyte(spc_header_addr+0x100+0x6c);
if(!(flg & 0x20) && (edl & 0x0f)) {
int echo_start = esa << 8;
int echo_length = (edl & 0x0f) << 11;
printf("clearing echo buffer %04x-%04x...\n", echo_start, echo_start+echo_length-1);
sram_memset(spc_data_addr+echo_start, echo_length, 0);
}
return (uint32_t)filesize;
}
