static void configure_time_trigger_for_ssc(uint32_t ssc_trigger_hz)
{
#if 0
gpio_configure_pin(PIO_PA12_IDX, PIO_PERIPH_B);
pmc_enable_periph_clk(ID_PWM);
/* Disable PWM channels */
pwm_channel_disable(PWM, PWM_CHANNEL_1);
/* Set PWM clock A as PWM_FREQUENCY*PERIOD_VALUE (clock B is not used) */
pwm_clock_t clock_setting = {
.ul_clka = 1000 * 100,
.ul_clkb = 0,
.ul_mck = sysclk_get_cpu_hz()
};
pwm_init(PWM, &clock_setting);
pwm_channel_t g_pwm_channel;
/* Period is left-aligned */
g_pwm_channel.alignment = PWM_ALIGN_LEFT;
/* Output waveform starts at a low level */
g_pwm_channel.polarity = PWM_LOW;
/* Use PWM clock A as source clock */
g_pwm_channel.ul_prescaler = PWM_CMR_CPRE_CLKA;
/* Period value of output waveform */
g_pwm_channel.ul_period = 100;
/* Duty cycle value of output waveform */
g_pwm_channel.ul_duty = 50;
g_pwm_channel.channel = PWM_CHANNEL_1;
pwm_channel_init(PWM, &g_pwm_channel);
/* Disable channel counter event interrupt */
pwm_channel_disable_interrupt(PWM, PWM_CHANNEL_1, 0);
pwm_channel_enable(PWM, PWM_CHANNEL_1);
#endif
uint32_t ul_div = 0;
uint32_t ul_tc_clks = 0;
uint32_t ul_sysclk = sysclk_get_cpu_hz();
pmc_set_writeprotect(false);
// Enable peripheral clock.
pmc_enable_periph_clk(CONF_SSC_CLOCK_SOURCE_ID);
// TIOA configuration
// gpio_configure_pin(PIN_TC0_TIOA0, PIN_TC0_TIOA0_FLAGS);
// tc_set_writeprotect(TC2, true);
tc_set_writeprotect(CONF_SSC_CLOCK_TC, false);
// Configure TC for a 1Hz frequency and trigger on RC compare.
tc_find_mck_divisor(ssc_trigger_hz, ul_sysclk, &ul_div, &ul_tc_clks, ul_sysclk);
tc_init(CONF_SSC_CLOCK_TC, CONF_SSC_CLOCK_CHANNEL, ul_tc_clks | TC_CMR_WAVSEL_UP_RC | TC_CMR_WAVE | TC_CMR_ACPA_CLEAR | TC_CMR_ACPC_SET);
uint32_t tmp_val = (ul_sysclk / ul_div) / ssc_trigger_hz;
tc_write_ra(CONF_SSC_CLOCK_TC, CONF_SSC_CLOCK_CHANNEL, tmp_val / 2);
tc_write_rc(CONF_SSC_CLOCK_TC, CONF_SSC_CLOCK_CHANNEL, tmp_val);
// Start the Timer.
tc_start(CONF_SSC_CLOCK_TC, CONF_SSC_CLOCK_CHANNEL);
}
void tm_stick_init(uint32_t bus_speed_hz) {
if(g_tm_stick_data.mutex == NULL) {
g_tm_stick_data.mutex = xSemaphoreCreateMutex();
}
if(g_tm_stick_data.rtos_task_semaphore == NULL) {
vSemaphoreCreateBinary(g_tm_stick_data.rtos_task_semaphore);
}
configure_time_trigger_for_ssc(1000);
sysclk_enable_peripheral_clock(ID_SSC);
ssc_reset(SSC);
// Do not go over 1MHz, the pulse will be too long and extend over to the next clock's rising edge (The spec. sheet of 4021BCM does not really list the operation times of 3.3V operation.
// I tested a couple of speeds.... at 1.25MHz, I found that it sometimes misses some pulses.
if(bus_speed_hz > TM_STICK_MAX_BUS_SPEED){
bus_speed_hz = TM_STICK_MAX_BUS_SPEED;
}
ssc_set_clock_divider(SSC, bus_speed_hz, sysclk_get_cpu_hz());
clock_opt_t rx_clk_opt = {
.ul_cks = SSC_RCMR_CKS_MCK,
.ul_cko = SSC_RCMR_CKO_TRANSFER,
// TODO: Fix the SSC clock for some reason shift 1/2 clock pulse position.
// This makes the button results shift one position to the right. So we have to change rising/falling edge to "correct" it (oh, well, "hack" around it).
// Don't know why.
// One possible patch up is to use a pin to signal which one is desired to determine which of the following settings to use..
#if defined(CONF_BOARD_ARDUINO_DUE)
.ul_cki = 0, //SSC_RCMR_CKI,
#else
.ul_cki = SSC_RCMR_CKI,
#endif
.ul_ckg = SSC_RCMR_CKG_CONTINUOUS,
.ul_start_sel = SSC_RCMR_START_RF_FALLING,
.ul_period = 0,
.ul_sttdly = 0
};
data_frame_opt_t rx_data_frame_opt = {
.ul_datlen = 23,
.ul_msbf = 0, //SSC_RFMR_MSBF,
.ul_fsos = SSC_RFMR_FSOS_NONE,
.ul_datnb = 0,
.ul_fsedge = SSC_RFMR_FSEDGE_NEGATIVE,
.ul_fslen = 0,
.ul_fslen_ext = 0
};
ssc_set_receiver(SSC, &rx_clk_opt, &rx_data_frame_opt);
ssc_enable_interrupt(SSC, SSC_IER_RXRDY);
// It is VERY IMPORTANT to set the priority of the interrupt to conform to what FreeRTOS needs because we are calling FreeRTOS interrupt-safe APIs (those *FromISR) from within interrupt handlers.
// If we don't do this, if would work at the beginning, and then eventually the whole thing will come crashing down.
// And it's not gonna crash even after millions of interrupts are handled. It will come crashing down in some very weird place after you start using another interrupt handler, like the pio handlers, and only after some handlling...
// And, it will appear random. You press the button a couple of times, it dies. Then, at other times, you press and hold the button, etc. etc. Each time will be different.
// You would be suspecting your stack overflowed, your code does a wild pointer, etc. etc. It's very difficult to debug. Trust me, you don't wanna go there.
NVIC_ClearPendingIRQ(SSC_IRQn);
NVIC_SetPriority(SSC_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
NVIC_EnableIRQ(SSC_IRQn);
ssc_enable_rx(SSC);
}
void SSC_Handler( void ) {
portBASE_TYPE xHigherTaskWoken = pdFALSE;
uint32_t* in_data_buf = (uint32_t*)g_tm_stick_data.data;
uint32_t in_data = 0;
static uint32_t previous_in_data = 0;
static bool is_first_time = true;
// calculate the mask needed to wipe off extra high bit junk.
static uint32_t mask = 0xFFFFFFFF;
if(is_first_time) {
for(int i = 4; i > TM_STICK_NUM_DATA_BYTES; i--) {
mask = mask >> 8;
}
}
if(ssc_is_rx_ready(SSC) == SSC_RC_YES) {
xSemaphoreTakeFromISR(g_tm_stick_data.mutex, &xHigherTaskWoken);
in_data = SSC->SSC_RHR;
// in_data >>= 1; // No idea why it always reads 25bits (one too many bit at the end LSB), instead of 24 I told it to. Therefore, we shift it off.
in_data = ~in_data; // reverse it. So, now 1 is on, 0 is off.
in_data &= mask;
// Glitch filtering below.
if(is_first_time
|| (previous_in_data ^ in_data) == 0) {
is_first_time = false;
*in_data_buf = in_data;
}
previous_in_data = in_data;
xSemaphoreGiveFromISR(g_tm_stick_data.mutex, &xHigherTaskWoken);
xHigherTaskWoken = pdFALSE;
xSemaphoreGiveFromISR(g_tm_stick_data.rtos_task_semaphore, &xHigherTaskWoken); // if there is an RTOS waiting for the ADC task mutex, wake it up.
portEND_SWITCHING_ISR(xHigherTaskWoken);
}
}
#ifdef __cplusplus
}
/**
* \brief Test Synchronous Serial Controller.
* This test sets SSC module in the loop mode and check the receiver data
* whether it's the same as the transmit data.
*
* \param test Current test case.
*/
static void run_ssc_test(const struct test_case *test)
{
uint32_t ul_mck;
clock_opt_t tx_clk_option;
clock_opt_t rx_clk_option;
data_frame_opt_t rx_data_frame_option;
data_frame_opt_t tx_data_frame_option;
/* Initialize the local variable. */
ul_mck = 0;
memset((uint8_t *)&rx_clk_option, 0, sizeof(clock_opt_t));
memset((uint8_t *)&rx_data_frame_option, 0, sizeof(data_frame_opt_t));
memset((uint8_t *)&tx_clk_option, 0, sizeof(clock_opt_t));
memset((uint8_t *)&tx_data_frame_option, 0, sizeof(data_frame_opt_t));
/* Initialize the SSC module and work in loop mode. */
pmc_enable_periph_clk(ID_SSC);
ssc_reset(SSC);
ul_mck = sysclk_get_cpu_hz();
ssc_set_clock_divider(SSC, SSC_BIT_RATE, ul_mck);
/* Transmitter clock mode configuration. */
tx_clk_option.ul_cks = SSC_TCMR_CKS_MCK;
tx_clk_option.ul_cko = SSC_TCMR_CKO_CONTINUOUS;
tx_clk_option.ul_cki = 0;
tx_clk_option.ul_ckg = SSC_TCMR_CKG_NONE;
tx_clk_option.ul_start_sel = SSC_TCMR_START_CONTINUOUS;
tx_clk_option.ul_sttdly = 0;
tx_clk_option.ul_period = 0;
/* Transmitter frame mode configuration. */
tx_data_frame_option.ul_datlen = BIT_LEN_PER_CHANNEL - 1;
tx_data_frame_option.ul_msbf = SSC_TFMR_MSBF;
tx_data_frame_option.ul_datnb = 0;
tx_data_frame_option.ul_fslen = 0;
tx_data_frame_option.ul_fslen_ext = 0;
tx_data_frame_option.ul_fsos = SSC_TFMR_FSOS_TOGGLING;
tx_data_frame_option.ul_fsedge = SSC_TFMR_FSEDGE_POSITIVE;
/* Configure the SSC transmitter. */
ssc_set_transmitter(SSC, &tx_clk_option, &tx_data_frame_option);
/* Receiver clock mode configuration. */
rx_clk_option.ul_cks = SSC_RCMR_CKS_TK;
rx_clk_option.ul_cko = SSC_RCMR_CKO_NONE;
rx_clk_option.ul_cki = 0;
rx_clk_option.ul_ckg = SSC_TCMR_CKG_NONE;
rx_clk_option.ul_start_sel = SSC_RCMR_START_RF_EDGE;
rx_clk_option.ul_sttdly = 0;
rx_clk_option.ul_period = 0;
/* Receiver frame mode configuration. */
rx_data_frame_option.ul_datlen = BIT_LEN_PER_CHANNEL - 1;
rx_data_frame_option.ul_msbf = SSC_TFMR_MSBF;
rx_data_frame_option.ul_datnb = 0;
rx_data_frame_option.ul_fslen = 0;
rx_data_frame_option.ul_fslen_ext = 0;
rx_data_frame_option.ul_fsos = SSC_TFMR_FSOS_NONE;
rx_data_frame_option.ul_fsedge = SSC_TFMR_FSEDGE_POSITIVE;
/* Configure the SSC receiver. */
ssc_set_receiver(SSC, &rx_clk_option, &rx_data_frame_option);
/* Enable the loop mode. */
ssc_set_loop_mode(SSC);
/* Enable the tx and rx function. */
ssc_enable_rx(SSC);
ssc_enable_tx(SSC);
/* Configure the RX interrupt. */
ssc_enable_interrupt(SSC, SSC_IER_RXRDY);
/* Enable SSC interrupt line from the core */
NVIC_DisableIRQ(SSC_IRQn);
NVIC_ClearPendingIRQ(SSC_IRQn);
NVIC_SetPriority(SSC_IRQn, SSC_IRQ_PRIO);
NVIC_EnableIRQ(SSC_IRQn);
for (g_uc_tx_index = 0; g_uc_tx_index < BUFFER_SIZE; g_uc_tx_index++) {
ssc_write(SSC, g_uc_tx_buff[g_uc_tx_index]);
}
while (!g_uc_rx_done) {
}
test_assert_true(test, (memcmp(g_uc_rx_buff, g_uc_tx_buff, BUFFER_SIZE) == 0),
"Test: SSC received data is not the same as the transmit data!");
}
