void pic16C5x_init(void)
{
int cpu = cpu_getactivecpu();
state_save_register_INT8("pic16C5x", cpu, "Old_Data", &old_data, 1);
state_save_register_UINT8("pic16C5x", cpu, "W", &R.W, 1);
state_save_register_UINT8("pic16C5x", cpu, "ALU", &R.ALU, 1);
state_save_register_UINT8("pic16C5x", cpu, "Option", &R.OPTION, 1);
state_save_register_UINT8("pic16C5x", cpu, "TRISA", &R.TRISA, 1);
state_save_register_UINT8("pic16C5x", cpu, "TRISB", &R.TRISB, 1);
state_save_register_UINT8("pic16C5x", cpu, "TRISC", &R.TRISC, 1);
state_save_register_UINT8("pic16C5x", cpu, "PORTA", &R.PORTA, 1);
state_save_register_UINT8("pic16C5x", cpu, "PORTB", &R.PORTB, 1);
state_save_register_UINT8("pic16C5x", cpu, "PORTC", &R.PORTC, 1);
state_save_register_UINT8("pic16C5x", cpu, "Old_T0", &old_T0, 1);
state_save_register_UINT8("pic16C5x", cpu, "STR", &R.STATUS, 1);
state_save_register_UINT8("pic16C5x", cpu, "RAM_mask", &picRAMmask, 1);
state_save_register_UINT16("pic16C5x", cpu, "WDT", &R.WDT, 1);
state_save_register_UINT16("pic16C5x", cpu, "Prescaler", &R.prescaler, 1);
state_save_register_UINT16("pic16C5x", cpu, "Stack0", &R.STACK[0], 1);
state_save_register_UINT16("pic16C5x", cpu, "Stack1", &R.STACK[1], 1);
state_save_register_UINT16("pic16C5x", cpu, "PC", &R.PC, 1);
state_save_register_UINT16("pic16C5x", cpu, "PrevPC", &R.PREVPC, 1);
state_save_register_UINT16("pic16C5x", cpu, "Config", &R.CONFIG, 1);
state_save_register_UINT32("pic16C5x", cpu, "Opcode", &R.opcode.d, 1);
state_save_register_INT32("pic16C5x", cpu, "Delay_Timer", &delay_timer, 1);
state_save_register_INT32("pic16C5x", cpu, "PIC_model", &picmodel, 1);
state_save_register_INT32("pic16C5x", cpu, "Reset_Vector", &pic16C5x_reset_vector, 1);
}
int cpuint_init(void)
{
int cpunum;
int irqline;
/* loop over all CPUs */
for (cpunum = 0; cpunum < cpu_gettotalcpu(); cpunum++)
{
/* reset the IRQ lines */
for (irqline = 0; irqline < MAX_IRQ_LINES; irqline++)
{
irq_line_state[cpunum][irqline] = CLEAR_LINE;
interrupt_vector[cpunum][irqline] =
irq_line_vector[cpunum][irqline] = cpunum_default_irq_vector(cpunum);
}
/* reset the IRQ event queues */
irq_event_index[cpunum] = 0;
}
/* set up some stuff to save */
state_save_set_current_tag(0);
state_save_register_UINT8("cpu", 0, "irq enable", interrupt_enable, cpu_gettotalcpu());
state_save_register_INT32("cpu", 0, "irq vector", &interrupt_vector[0][0],cpu_gettotalcpu() * MAX_IRQ_LINES);
state_save_register_UINT8("cpu", 0, "irqline state", &irq_line_state[0][0], cpu_gettotalcpu() * MAX_IRQ_LINES);
state_save_register_INT32("cpu", 0, "irqline vector", &irq_line_vector[0][0], cpu_gettotalcpu() * MAX_IRQ_LINES);
return 0;
}
void hd63705_init(void)
{
int cpu = cpu_getactivecpu();
state_register("hd63705");
state_save_register_INT32("hd63705",cpu,"IRQ1_STATE", &m6805.irq_state[0], 1);
state_save_register_INT32("hd63705",cpu,"IRQ2_STATE", &m6805.irq_state[1], 1);
state_save_register_INT32("hd63705",cpu,"TIMER1_STATE", &m6805.irq_state[2], 1);
state_save_register_INT32("hd63705",cpu,"TIMER2_STATE", &m6805.irq_state[3], 1);
state_save_register_INT32("hd63705",cpu,"TIMER3_STATE", &m6805.irq_state[4], 1);
state_save_register_INT32("hd63705",cpu,"PCI_STATE", &m6805.irq_state[5], 1);
state_save_register_INT32("hd63705",cpu,"SCI_STATE", &m6805.irq_state[6], 1);
state_save_register_INT32("hd63705",cpu,"ADCONV_STATE", &m6805.irq_state[7], 1);
}
int cpu_init(void)
{
int cpunum;
/* initialize the interfaces first */
if (cpuintrf_init())
return 1;
/* loop over all our CPUs */
for (cpunum = 0; cpunum < MAX_CPU; cpunum++)
{
int cputype = Machine->drv->cpu[cpunum].cpu_type;
/* if this is a dummy, stop looking */
if (cputype == CPU_DUMMY)
break;
/* set the save state tag */
state_save_set_current_tag(cpunum + 1);
/* initialize the cpuinfo struct */
memset(&cpu[cpunum], 0, sizeof(cpu[cpunum]));
cpu[cpunum].suspend = SUSPEND_REASON_RESET;
cpu[cpunum].clockscale = cputype_get_interface(cputype)->overclock;
/* compute the cycle times */
sec_to_cycles[cpunum] = cpu[cpunum].clockscale * Machine->drv->cpu[cpunum].cpu_clock;
cycles_to_sec[cpunum] = 1.0 / sec_to_cycles[cpunum];
/* initialize this CPU */
if (cpuintrf_init_cpu(cpunum, cputype))
return 1;
}
/* compute the perfect interleave factor */
compute_perfect_interleave();
/* save some stuff in tag 0 */
state_save_set_current_tag(0);
state_save_register_INT32("cpu", 0, "watchdog count", &watchdog_counter, 1);
/* reset the IRQ lines and save those */
if (cpuint_init())
return 1;
return 0;
}
static void AY8910_statesave(int chip)
{
struct AY8910 *PSG = &AYPSG[chip];
state_save_register_INT32("AY8910", chip, "register_latch", &PSG->register_latch, 1);
state_save_register_UINT8("AY8910", chip, "Regs", PSG->Regs, 8);
state_save_register_INT32("AY8910", chip, "lastEnable", &PSG->lastEnable, 1);
state_save_register_INT32("AY8910", chip, "PeriodA", &PSG->PeriodA, 1);
state_save_register_INT32("AY8910", chip, "PeriodB", &PSG->PeriodB, 1);
state_save_register_INT32("AY8910", chip, "PeriodC", &PSG->PeriodC, 1);
state_save_register_INT32("AY8910", chip, "PeriodN", &PSG->PeriodN, 1);
state_save_register_INT32("AY8910", chip, "PeriodE", &PSG->PeriodE, 1);
state_save_register_INT32("AY8910", chip, "CountA", &PSG->CountA, 1);
state_save_register_INT32("AY8910", chip, "CountB", &PSG->CountB, 1);
state_save_register_INT32("AY8910", chip, "CountC", &PSG->CountC, 1);
state_save_register_INT32("AY8910", chip, "CountN", &PSG->CountN, 1);
state_save_register_INT32("AY8910", chip, "CountE", &PSG->CountE, 1);
state_save_register_UINT32("AY8910", chip, "VolA", &PSG->VolA, 1);
state_save_register_UINT32("AY8910", chip, "VolB", &PSG->VolB, 1);
state_save_register_UINT32("AY8910", chip, "VolC", &PSG->VolC, 1);
state_save_register_UINT32("AY8910", chip, "VolE", &PSG->VolE, 1);
state_save_register_UINT8("AY8910", chip, "EnvelopeA", &PSG->EnvelopeA, 1);
state_save_register_UINT8("AY8910", chip, "EnvelopeB", &PSG->EnvelopeB, 1);
state_save_register_UINT8("AY8910", chip, "EnvelopeC", &PSG->EnvelopeC, 1);
state_save_register_UINT8("AY8910", chip, "OutputA", &PSG->OutputA, 1);
state_save_register_UINT8("AY8910", chip, "OutputB", &PSG->OutputB, 1);
state_save_register_UINT8("AY8910", chip, "OutputC", &PSG->OutputC, 1);
state_save_register_UINT8("AY8910", chip, "OutputN", &PSG->OutputN, 1);
state_save_register_INT8("AY8910", chip, "CountEnv", &PSG->CountEnv, 1);
state_save_register_UINT8("AY8910", chip, "Hold", &PSG->Hold, 1);
state_save_register_UINT8("AY8910", chip, "Alternate", &PSG->Alternate, 1);
state_save_register_UINT8("AY8910", chip, "Attack", &PSG->Attack, 1);
state_save_register_UINT8("AY8910", chip, "Holding", &PSG->Holding, 1);
state_save_register_INT32("AY8910", chip, "RNG", &PSG->RNG, 1);
}
/* Generate interrupts */
static void Interrupt(void)
{
/* the 6805 latches interrupt requests internally, so we don't clear */
/* pending_interrupts until the interrupt is taken, no matter what the */
/* external IRQ pin does. */
#if (HAS_HD63705)
if( (m6805.pending_interrupts & (1<<HD63705_INT_NMI)) != 0)
{
PUSHWORD(m6805.pc);
PUSHBYTE(m6805.x);
PUSHBYTE(m6805.a);
PUSHBYTE(m6805.cc);
SEI;
/* no vectors supported, just do the callback to clear irq_state if needed */
if (m6805.irq_callback)
(*m6805.irq_callback)(0);
RM16( 0x1ffc, &pPC);
change_pc(PC);
m6805.pending_interrupts &= ~(1<<HD63705_INT_NMI);
m6805_ICount -= 11;
}
else if( (m6805.pending_interrupts & ((1<<M6805_IRQ_LINE)|HD63705_INT_MASK)) != 0 ) {
if ( (CC & IFLAG) == 0 ) {
#else
if( (m6805.pending_interrupts & (1<<M6805_IRQ_LINE)) != 0 ) {
if ( (CC & IFLAG) == 0 ) {
#endif
{
/* standard IRQ */
/*#if (HAS_HD63705) */
/* if(SUBTYPE!=SUBTYPE_HD63705) */
/*#endif */
/* PC |= ~AMASK; */
PUSHWORD(m6805.pc);
PUSHBYTE(m6805.x);
PUSHBYTE(m6805.a);
PUSHBYTE(m6805.cc);
SEI;
/* no vectors supported, just do the callback to clear irq_state if needed */
if (m6805.irq_callback)
(*m6805.irq_callback)(0);
#if (HAS_HD63705)
if(SUBTYPE==SUBTYPE_HD63705)
{
/* Need to add emulation of other interrupt sources here KW-2/4/99 */
/* This is just a quick patch for Namco System 2 operation */
if((m6805.pending_interrupts&(1<<HD63705_INT_IRQ1))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_IRQ1);
RM16( 0x1ff8, &pPC);
change_pc(PC);
}
else if((m6805.pending_interrupts&(1<<HD63705_INT_IRQ2))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_IRQ2);
RM16( 0x1fec, &pPC);
change_pc(PC);
}
else if((m6805.pending_interrupts&(1<<HD63705_INT_ADCONV))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_ADCONV);
RM16( 0x1fea, &pPC);
change_pc(PC);
}
else if((m6805.pending_interrupts&(1<<HD63705_INT_TIMER1))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_TIMER1);
RM16( 0x1ff6, &pPC);
change_pc(PC);
}
else if((m6805.pending_interrupts&(1<<HD63705_INT_TIMER2))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_TIMER2);
RM16( 0x1ff4, &pPC);
change_pc(PC);
}
else if((m6805.pending_interrupts&(1<<HD63705_INT_TIMER3))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_TIMER3);
RM16( 0x1ff2, &pPC);
change_pc(PC);
}
else if((m6805.pending_interrupts&(1<<HD63705_INT_PCI))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_PCI);
RM16( 0x1ff0, &pPC);
change_pc(PC);
}
else if((m6805.pending_interrupts&(1<<HD63705_INT_SCI))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_SCI);
RM16( 0x1fee, &pPC);
change_pc(PC);
}
}
else
#endif
{
RM16( 0xffff - 5, &pPC );
change_pc(PC);
}
} /* CC & IFLAG */
m6805.pending_interrupts &= ~(1<<M6805_IRQ_LINE);
}
m6805_ICount -= 11;
}
}
static void state_register(const char *type)
{
int cpu = cpu_getactivecpu();
state_save_register_UINT8(type, cpu, "A", &A, 1);
state_save_register_UINT16(type, cpu, "PC", &PC, 1);
state_save_register_UINT16(type, cpu, "S", &S, 1);
state_save_register_UINT8(type, cpu, "X", &X, 1);
state_save_register_UINT8(type, cpu, "CC", &CC, 1);
state_save_register_UINT16(type, cpu, "PENDING", &m6805.pending_interrupts, 1);
state_save_register_INT32(type, cpu, "IRQ_STATE", &m6805.irq_state[0], 1);
}
static void m6805_init(void)
{
state_register("m6805");
}
