static void __init qemu_e500_setup_arch(void)
{
ppc_md.progress("qemu_e500_setup_arch()", 0);
fsl_pci_assign_primary();
swiotlb_detect_4g();
mpc85xx_smp_init();
}
/*
* Setup the architecture
*/
void __init corenet_gen_setup_arch(void)
{
mpc85xx_smp_init();
swiotlb_detect_4g();
pr_info("%s board\n", ppc_md.name);
mpc85xx_qe_init();
}
/*
* Setup the architecture
*/
void __init corenet_gen_setup_arch(void)
{
mpc85xx_smp_init();
swiotlb_detect_4g();
pr_info("%s board from Freescale Semiconductor\n", ppc_md.name);
mpc85xx_qe_init();
}
/*
* Setup the architecture
*/
static void __init mpc85xx_ds_setup_arch(void)
{
if (ppc_md.progress)
ppc_md.progress("mpc85xx_ds_setup_arch()", 0);
swiotlb_detect_4g();
fsl_pci_assign_primary();
mpc85xx_ds_uli_init();
mpc85xx_smp_init();
printk("MPC85xx DS board from Freescale Semiconductor\n");
}
static void __init mpc85xx_mds_setup_arch(void)
{
if (ppc_md.progress)
ppc_md.progress("mpc85xx_mds_setup_arch()", 0);
mpc85xx_smp_init();
mpc85xx_mds_qe_init();
fsl_pci_assign_primary();
swiotlb_detect_4g();
}
/*
* Setup the architecture
*/
void __init corenet_ds_setup_arch(void)
{
mpc85xx_smp_init();
#if defined(CONFIG_PCI) && defined(CONFIG_PPC64)
pci_devs_phb_init();
#endif
fsl_pci_assign_primary();
swiotlb_detect_4g();
pr_info("%s board from Freescale Semiconductor\n", ppc_md.name);
}
/*
* Setup the architecture
*/
static void __init p1022_rdk_setup_arch(void)
{
if (ppc_md.progress)
ppc_md.progress("p1022_rdk_setup_arch()", 0);
#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
diu_ops.set_pixel_clock = p1022rdk_set_pixel_clock;
diu_ops.valid_monitor_port = p1022rdk_valid_monitor_port;
#endif
mpc85xx_smp_init();
fsl_pci_assign_primary();
swiotlb_detect_4g();
pr_info("Freescale / iVeia P1022 RDK reference board\n");
}
/*
* Setup the architecture
*/
void __init corenet_gen_setup_arch(void)
{
mpc85xx_smp_init();
swiotlb_detect_4g();
#if defined(CONFIG_FSL_PCI) && defined(CONFIG_ZONE_DMA32)
/*
* Inbound windows don't cover the full lower 4 GiB
* due to conflicts with PCICSRBAR and outbound windows,
* so limit the DMA32 zone to 2 GiB, to allow consistent
* allocations to succeed.
*/
limit_zone_pfn(ZONE_DMA32, 1UL << (31 - PAGE_SHIFT));
#endif
pr_info("%s board\n", ppc_md.name);
mpc85xx_qe_init();
}
static void __init
mpc86xx_hpcn_setup_arch(void)
{
if (ppc_md.progress)
ppc_md.progress("mpc86xx_hpcn_setup_arch()", 0);
#ifdef CONFIG_PCI
ppc_md.pci_exclude_device = mpc86xx_exclude_device;
#endif
printk("MPC86xx HPCN board from Freescale Semiconductor\n");
#ifdef CONFIG_SMP
mpc86xx_smp_init();
#endif
fsl_pci_assign_primary();
swiotlb_detect_4g();
}
/*
* Setup the architecture
*/
static void __init p1022_ds_setup_arch(void)
{
if (ppc_md.progress)
ppc_md.progress("p1022_ds_setup_arch()", 0);
#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
diu_ops.set_monitor_port = p1022ds_set_monitor_port;
diu_ops.set_pixel_clock = p1022ds_set_pixel_clock;
diu_ops.valid_monitor_port = p1022ds_valid_monitor_port;
/*
* Disable the NOR and NAND flash nodes if there is video=fslfb...
* command-line parameter. When the DIU is active, the localbus is
* unavailable, so we have to disable these nodes before the MTD
* driver loads.
*/
if (fslfb) {
struct device_node *np =
of_find_compatible_node(NULL, NULL, "fsl,p1022-elbc");
if (np) {
struct device_node *np2;
of_node_get(np);
np2 = of_find_compatible_node(np, NULL, "cfi-flash");
if (np2) {
static struct property nor_status = {
.name = "status",
.value = "disabled",
.length = sizeof("disabled"),
};
/*
* of_update_property() is called before
* kmalloc() is available, so the 'new' object
* should be allocated in the global area.
* The easiest way is to do that is to
* allocate one static local variable for each
* call to this function.
*/
pr_info("p1022ds: disabling %s node",
np2->full_name);
of_update_property(np2, &nor_status);
of_node_put(np2);
}
of_node_get(np);
np2 = of_find_compatible_node(np, NULL,
"fsl,elbc-fcm-nand");
if (np2) {
static struct property nand_status = {
.name = "status",
.value = "disabled",
.length = sizeof("disabled"),
};
pr_info("p1022ds: disabling %s node",
np2->full_name);
of_update_property(np2, &nand_status);
of_node_put(np2);
}
of_node_put(np);
}
}
#endif
mpc85xx_smp_init();
fsl_pci_assign_primary();
swiotlb_detect_4g();
#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
indirect_access_pixis_probe();
#endif
pr_info("Freescale P1022 DS reference board\n");
}
machine_arch_initcall(p1022_ds, mpc85xx_common_publish_devices);
machine_arch_initcall(p1022_ds, swiotlb_setup_bus_notifier);
/*
* Called very early, device-tree isn't unflattened
*/
static int __init p1022_ds_probe(void)
{
unsigned long root = of_get_flat_dt_root();
return of_flat_dt_is_compatible(root, "fsl,p1022ds");
}
define_machine(p1022_ds) {
.name = "P1022 DS",
.probe = p1022_ds_probe,
.setup_arch = p1022_ds_setup_arch,
.init_IRQ = p1022_ds_pic_init,
#ifdef CONFIG_PCI
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
#endif
.get_irq = mpic_get_irq,
.restart = fsl_rstcr_restart,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};