void
main(int argc, char **argv)
{
int n;
int dopts = 0;
int dovb = 0;
int dosigs = 0;
extern int optind;
chname = 0;
while((n = getopt(argc, argv, "bfkprstv")) != -1)
switch(n)
{
case 'k': chname = 1; break;
case 't': chname = -1; break;
case 'p': dopts = 1; break;
case 'v': dovb = 1; break;
case 'b': boxed = 1; break;
case 'r': ruled = 0; break;
case 'f': framed = 1; break;
case 's': dosigs = 1; break;
case '?': break;
}
fizzinit();
f_init(&b);
if(optind == argc)
argv[--optind] = "/dev/stdin";
for(; optind < argc; optind++)
if(n = f_crack(argv[optind], &b)){
fprint(1, "%s: %d errors\n", *argv, n);
exit(1);
}
fizzplane(&b);
if(n = fizzplace()){
/* complain but don't exit */
fprint(2, "%d chips unplaced\n", n);
}
if(fizzprewrap())
dosigs = 0;
draw(dopts, dovb);
if(dosigs){
extern Signal *maxsig;
extern void tsp(Signal *);
symtraverse(S_SIGNAL, netlen);
if(maxsig && ((maxsig->type & VSIG) != VSIG) && (maxsig->n >= MAXNET)){
fprint(1, "net %s is too big (%d>=%d)\n", maxsig->name,
maxsig->n, MAXNET);
exits("bignet");
}
wwires = 0;
wwraplen = 0;
symtraverse(S_SIGNAL, tsp);
symtraverse(S_SIGNAL, drawsig);
}
exit(0);
}
void
draw(int dopts, int dovb)
{
register i, j;
fprint(1, "open\n");
fprint(1, "range %d %d %d %d\n", b.prect.min.x-INCH, b.prect.min.y-INCH,
b.prect.max.x+INCH, b.prect.max.y+INCH);
fprint(1, ".color FCW\n");
fprint(1, ".color P6\n");
if (ruled) {
drawrule();
drawalign();
}
if (framed) drawframe();
symtraverse(S_CHIP, drawchip);
if(dopts)
pintraverse(drawpin);
if(dovb)
for(i = 0; i < 6; i++)
for(j = 0; j < b.v[i].npins; j++)
drawvbpin(&b.v[i].pins[j], i);
fprint(1, "close\n");
}
void
execinit(void)
{
char **p;
nextv = 0;
for(p = myenv; *p; p++)
envinsert(*p, stow(""));
symtraverse(S_VAR, ecopy);
envinsert(0, 0);
}
void
main(int argc, char **argv)
{
Board b;
int n;
char *fname;
ARGBEGIN{
case 'b':
++bflag; /* show bottom view */
break;
case 'g':
++gflag; /* show 100 mil grid */
break;
case 'p':
if(npkg < NPKG)
pkgnames[npkg++] = ARGF();
break;
default:
fprint(2, "usage: %s [-b] [-p name] [files...]\n", argv0);
exits("usage");
}ARGEND
f_init(&b);
#ifdef PLAN9
if(*argv)
fname = *argv++;
else
fname = "/fd/0";
#endif
#ifndef PLAN9
if(*argv)
fname = *argv++;
else
fname = "/dev/stdin";
#endif
do{
if(n = f_crack(fname, &b)){
fprint(2, "%s: %d errors\n", fname, n);
exits("errors");
}
}while(fname = *argv++); /* assign = */
symtraverse(S_PACKAGE, picpr);
exits(0);
}
void
main(int argc, char **argv)
{
int n;
extern long nph;
int doundef = 0;
int dow = 0;
char *chname = 0;
char *pkname = 0;
extern int optind;
extern char *optarg;
extern Signal *maxsig;
while((n = getopt(argc, argv, "uwp:c:")) != -1)
switch(n)
{
case 'u': doundef = 1; break;
case 'w': dow = 1; break;
case 'c': chname = optarg; break;
case 'p': pkname = optarg; break;
case '?': break;
}
fizzinit();
f_init(&b);
if(optind == argc)
argv[--optind] = "/dev/stdin";
for(; optind < argc; optind++)
if(n = f_crack(argv[optind], &b)){
fprint(1, "%s: %d errors\n", argv[optind], n);
exit(1);
}
if(b.name)
fprint(1, "Board %s:\n", b.name);
else
fprint(1, "Warning: no board name\n");
if(n = fizzplace()){
fprint(1, "%d chips unplaced\n", n);
if(doundef)
symtraverse(S_CHIP, prundef);
exit(1);
}
cutout(&b);
fizzplane(&b);
if(pkname)
prpkg((Package *)symlook(pkname, S_PACKAGE, (void *)0));
if(chname)
prchip((Chip *)symlook(chname, S_CHIP, (void *)0));
if(dow){
if(fizzprewrap())
exit(1);
symtraverse(S_SIGNAL, netlen);
if(maxsig && ((maxsig->type & VSIG) != VSIG) && (maxsig->n >= MAXNET)){
fprint(1, "net %s is too big (%d>=%d)\n", maxsig->name,
maxsig->n, MAXNET);
exit(1);
}
setup();
symtraverse(S_CHIP, chkpins);
}
symtraverse(S_PACKAGE, chkpkgpins);
exit(0);
}
void
main(int argc, char **argv)
{
int n;
extern long nph;
int doundef = 0;
int dow = 0;
int dosignal = 0;
float ratio;
extern int optind;
extern char *optarg;
extern Signal *maxsig;
while((n = getopt(argc, argv, "lqsuvz:adkw:c:")) != -1)
switch(n)
{
case 'k': konstant = atof(optarg); break;
case 'a': width = AWG(atof(optarg)); break;
case 'd': epsilon = atof(optarg); break;
case 'l': dolength = 1; break;
case 'q': quiet = 1; break;
case 's': dosignal = 1; break;
case 'u': doundef = 1; break;
case 'v': dow = 1; break;
case 'w': width = atof(optarg); break;
case 'z': Z0 = atof(optarg); break;
case '?': break;
}
fizzinit();
f_init(&b);
if(optind == argc)
argv[--optind] = "/dev/stdin";
for(; optind < argc; optind++)
if(n = f_crack(argv[optind], &b)){
fprint(1, "%s: %d errors\n", argv[optind], n);
exit(1);
}
if(b.name)
fprint(1, "Board %s:\n", b.name);
else
fprint(1, "Warning: no board name\n");
if(n = fizzplace()){
fprint(1, "%d chips unplaced\n", n);
if(doundef)
symtraverse(S_CHIP, prundef);
exit(1);
}
cutout(&b);
fizzplane(&b);
if (fizzprewrap())
exit(1);
if (dow) symtraverse(S_SIGNAL, prwires);
symtraverse(S_SIGNAL, calclength);
if (dosignal) symtraverse(S_SIGNAL, prsignal);
pininit();
symtraverse(S_SIGNAL, insertpins);
/*
* ratio is 2 * h / d from Shibata & Ryuiti;
* L0 is from Terman's classic, but neglects skin effect (in microhenries / ft)
*/
ratio = exp((Z0 - 17.08) / 34.83);
L0 = 0.1404 * log10(2.0 * ratio) * 83.3333;
C0 = L0 / square(Z0);
fprint(2, "Capacitance=%f, inductance=%f, ns/ft=%f\n", C0, L0, 12.0*sqrt(C0*L0));
symtraverse(S_SIGNAL, cksignal);
exit(0);
}
void
dumpv(char *s)
{
Bprint(&bout, "%s:\n", s);
symtraverse(S_VAR, print1);
}
