/**
* \brief Test Synchronous clock
*
* This test enables source clock for main clock, sets CPU/HSB,
* PBA,PBB,PBC(if have), PBD(if have) division factor, and then check
* if the chip is set correctly.
*
* \note It's not easy to measure CPU/HSB,PBA... frequency, even through
* some chips have freqm module. Using external module may cause some
* reliability issue. Since synchronous clocks share the common root
* main clock, they only need set division factor. So we just test
* the related registers if set correctly after calling common clock
* service.
*
* \param test Current test case.
*/
static void run_sync_clock_test(const struct test_case *test)
{
bool status;
/* avoid Cppcheck Warning */
UNUSED(status);
sysclk_init();
//PBA clock set, usart can be used
usart_ready = 1;
#ifdef CONFIG_CPU_HZ
status = (CONFIG_CPU_HZ == sysclk_get_cpu_hz());
test_assert_true(test, status, "CPU clock set fail");
#endif
#ifdef CONFIG_PBA_HZ
status = (CONFIG_PBA_HZ == sysclk_get_pba_hz());
test_assert_true(test, status, "PBA clock set fail");
#endif
#ifdef CONFIG_PBB_HZ
status = (CONFIG_PBB_HZ == sysclk_get_pbb_hz());
test_assert_true(test, status, "PBB clock set fail");
#endif
#ifdef CONFIG_PBC_HZ
status = (CONFIG_PBC_HZ == sysclk_get_pbc_hz());
test_assert_true(test, status, "PBC clock set fail");
#endif
#ifdef CONFIG_PBD_HZ
status = (CONFIG_PBD_HZ == sysclk_get_pbd_hz());
test_assert_true(test, status, "PBD clock set fail");
#endif
}
/**
* \brief Retrieves the current rate in Hz of the Peripheral Bus clock attached
* to the specified peripheral.
*
* \param module Pointer to the module's base address.
*
* \return Frequency of the bus attached to the specified peripheral, in Hz.
*/
uint32_t sysclk_get_peripheral_bus_hz(const volatile void *module)
{
/* Fallthroughs intended for modules sharing the same peripheral bus. */
switch ((uintptr_t)module) {
case IISC_ADDR:
case SPI_ADDR:
case TC0_ADDR:
case TC1_ADDR:
case TWIM0_ADDR:
case TWIS0_ADDR:
case TWIM1_ADDR:
case TWIS1_ADDR:
case USART0_ADDR:
case USART1_ADDR:
case USART2_ADDR:
case USART3_ADDR:
case ADCIFE_ADDR:
case DACC_ADDR:
case ACIFC_ADDR:
case GLOC_ADDR:
case ABDACB_ADDR:
case TRNG_ADDR:
case PARC_ADDR:
case CATB_ADDR:
case TWIM2_ADDR:
case TWIM3_ADDR:
#if !SAM4LS
case LCDCA_ADDR:
#endif
return sysclk_get_pba_hz();
case HFLASHC_ADDR:
case HCACHE_ADDR:
case HMATRIX_ADDR:
case PDCA_ADDR:
case CRCCU_ADDR:
case USBC_ADDR:
case PEVC_ADDR:
return sysclk_get_pbb_hz();
case PM_ADDR:
case CHIPID_ADDR:
case SCIF_ADDR:
case FREQM_ADDR:
case GPIO_ADDR:
return sysclk_get_pbc_hz();
case BPM_ADDR:
case BSCIF_ADDR:
case AST_ADDR:
case WDT_ADDR:
case EIC_ADDR:
case PICOUART_ADDR:
return sysclk_get_pbd_hz();
default:
Assert(false);
return 0;
}
}
/*! \brief Initializes SD/MMC resources: GPIO, MCI and SD/MMC.
*/
static void sd_mmc_mci_resources_init(void)
{
static const gpio_map_t SD_MMC_MCI_GPIO_MAP = {
{SD_SLOT_8BITS_CLK_PIN, SD_SLOT_8BITS_CLK_FUNCTION}, // SD CLK.
{SD_SLOT_8BITS_CMD_PIN, SD_SLOT_8BITS_CMD_FUNCTION}, // SD CMD.
{SD_SLOT_8BITS_DATA0_PIN, SD_SLOT_8BITS_DATA0_FUNCTION}, // SD DAT[0].
{SD_SLOT_8BITS_DATA1_PIN, SD_SLOT_8BITS_DATA1_FUNCTION}, // DATA Pin.
{SD_SLOT_8BITS_DATA2_PIN, SD_SLOT_8BITS_DATA2_FUNCTION}, // DATA Pin.
{SD_SLOT_8BITS_DATA3_PIN, SD_SLOT_8BITS_DATA3_FUNCTION}, // DATA Pin.
{SD_SLOT_8BITS_DATA4_PIN, SD_SLOT_8BITS_DATA4_FUNCTION}, // DATA Pin.
{SD_SLOT_8BITS_DATA5_PIN, SD_SLOT_8BITS_DATA5_FUNCTION}, // DATA Pin.
{SD_SLOT_8BITS_DATA6_PIN, SD_SLOT_8BITS_DATA6_FUNCTION}, // DATA Pin.
{SD_SLOT_8BITS_DATA7_PIN, SD_SLOT_8BITS_DATA7_FUNCTION} // DATA Pin.
};
// MCI options.
static const mci_options_t MCI_OPTIONS = {
.card_speed = 400000,
.card_slot = SD_SLOT_8BITS, // Default card initialization.
};
// Assign I/Os to MCI.
gpio_enable_module(SD_MMC_MCI_GPIO_MAP,
sizeof(SD_MMC_MCI_GPIO_MAP) /
sizeof(SD_MMC_MCI_GPIO_MAP[0]));
// Enable pull-up for Card Detect.
gpio_enable_pin_pull_up(SD_SLOT_8BITS_CARD_DETECT);
// Enable pull-up for Write Protect.
gpio_enable_pin_pull_up(SD_SLOT_8BITS_WRITE_PROTECT);
sd_mmc_mci_init(&MCI_OPTIONS, sysclk_get_pbb_hz(), sysclk_get_cpu_hz());
}
void memories_initialization(void)
{
//-- Hmatrix bus configuration
// This improve speed performance
#ifdef AVR32_HMATRIXB
union {
unsigned long scfg;
avr32_hmatrixb_scfg_t SCFG;
} u_avr32_hmatrixb_scfg;
sysclk_enable_pbb_module(SYSCLK_HMATRIX);
// For the internal-flash HMATRIX slave, use last master as default.
u_avr32_hmatrixb_scfg.scfg =
AVR32_HMATRIXB.scfg[AVR32_HMATRIXB_SLAVE_FLASH];
u_avr32_hmatrixb_scfg.SCFG.defmstr_type =
AVR32_HMATRIXB_DEFMSTR_TYPE_LAST_DEFAULT;
AVR32_HMATRIXB.scfg[AVR32_HMATRIXB_SLAVE_FLASH] =
u_avr32_hmatrixb_scfg.scfg;
// For the internal-SRAM HMATRIX slave, use last master as default.
u_avr32_hmatrixb_scfg.scfg =
AVR32_HMATRIXB.scfg[AVR32_HMATRIXB_SLAVE_SRAM];
u_avr32_hmatrixb_scfg.SCFG.defmstr_type =
AVR32_HMATRIXB_DEFMSTR_TYPE_LAST_DEFAULT;
AVR32_HMATRIXB.scfg[AVR32_HMATRIXB_SLAVE_SRAM] =
u_avr32_hmatrixb_scfg.scfg;
# ifdef AVR32_HMATRIXB_SLAVE_EBI
// For the EBI HMATRIX slave, use last master as default.
u_avr32_hmatrixb_scfg.scfg =
AVR32_HMATRIXB.scfg[AVR32_HMATRIXB_SLAVE_EBI];
u_avr32_hmatrixb_scfg.SCFG.defmstr_type =
AVR32_HMATRIXB_DEFMSTR_TYPE_LAST_DEFAULT;
AVR32_HMATRIXB.scfg[AVR32_HMATRIXB_SLAVE_EBI] =
u_avr32_hmatrixb_scfg.scfg;
# endif
#endif
#ifdef AVR32_HMATRIX
union {
unsigned long scfg;
avr32_hmatrix_scfg_t SCFG;
} u_avr32_hmatrix_scfg;
sysclk_enable_pbb_module(SYSCLK_HMATRIX);
// For the internal-flash HMATRIX slave, use last master as default.
u_avr32_hmatrix_scfg.scfg =
AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_FLASH];
u_avr32_hmatrix_scfg.SCFG.defmstr_type =
AVR32_HMATRIX_DEFMSTR_TYPE_LAST_DEFAULT;
AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_FLASH] =
u_avr32_hmatrix_scfg.scfg;
// For the internal-SRAM HMATRIX slave, use last master as default.
u_avr32_hmatrix_scfg.scfg =
AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_SRAM];
u_avr32_hmatrix_scfg.SCFG.defmstr_type =
AVR32_HMATRIX_DEFMSTR_TYPE_LAST_DEFAULT;
AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_SRAM] =
u_avr32_hmatrix_scfg.scfg;
# ifdef AVR32_HMATRIX_SLAVE_EBI
// For the EBI HMATRIX slave, use last master as default.
u_avr32_hmatrix_scfg.scfg =
AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_EBI];
u_avr32_hmatrix_scfg.SCFG.defmstr_type =
AVR32_HMATRIX_DEFMSTR_TYPE_LAST_DEFAULT;
AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_EBI] =
u_avr32_hmatrix_scfg.scfg;
# endif
#endif
#ifdef AVR32_HMATRIX_MASTER_USBB_DMA
union {
unsigned long mcfg;
avr32_hmatrix_mcfg_t MCFG;
} u_avr32_hmatrix_mcfg;
// For the USBB DMA HMATRIX master, use infinite length burst.
u_avr32_hmatrix_mcfg.mcfg =
AVR32_HMATRIX.mcfg[AVR32_HMATRIX_MASTER_USBB_DMA];
u_avr32_hmatrix_mcfg.MCFG.ulbt =
AVR32_HMATRIX_ULBT_INFINITE;
AVR32_HMATRIX.mcfg[AVR32_HMATRIX_MASTER_USBB_DMA] =
u_avr32_hmatrix_mcfg.mcfg;
// For the USBB DPRAM HMATRIX slave, use the USBB DMA as fixed default master.
u_avr32_hmatrix_scfg.scfg =
AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_USBB_DPRAM];
u_avr32_hmatrix_scfg.SCFG.fixed_defmstr =
AVR32_HMATRIX_MASTER_USBB_DMA;
u_avr32_hmatrix_scfg.SCFG.defmstr_type =
AVR32_HMATRIX_DEFMSTR_TYPE_FIXED_DEFAULT;
AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_USBB_DPRAM] =
u_avr32_hmatrix_scfg.scfg;
#endif
#if (defined AT45DBX_MEM) && (AT45DBX_MEM == ENABLE)
sysclk_enable_peripheral_clock(AT45DBX_SPI_MODULE);
at45dbx_init();
#endif
#if ((defined SD_MMC_MCI_0_MEM) && (SD_MMC_MCI_0_MEM == ENABLE)) \
|| ((defined SD_MMC_MCI_1_MEM) && (SD_MMC_MCI_1_MEM == ENABLE))
sysclk_enable_pbb_module(SYSCLK_MCI);
sysclk_enable_hsb_module(SYSCLK_DMACA);
sd_mmc_mci_init(SD_SLOT_8BITS, sysclk_get_pbb_hz(), sysclk_get_cpu_hz());
#endif
#if (defined SD_MMC_SPI_MEM) && (SD_MMC_SPI_MEM == ENABLE)
// SPI options.
spi_options_t spiOptions = {
.reg = SD_MMC_SPI_NPCS,
.baudrate = SD_MMC_SPI_MASTER_SPEED, // Defined in conf_sd_mmc_spi.h.
.bits = SD_MMC_SPI_BITS, // Defined in conf_sd_mmc_spi.h.
.spck_delay = 0,
.trans_delay = 0,
.stay_act = 1,
.spi_mode = 0,
.modfdis = 1
};
sysclk_enable_peripheral_clock(SD_MMC_SPI);
// If the SPI used by the SD/MMC is not enabled.
if (!spi_is_enabled(SD_MMC_SPI)) {
// Initialize as master.
spi_initMaster(SD_MMC_SPI, &spiOptions);
// Set selection mode: variable_ps, pcs_decode, delay.
spi_selectionMode(SD_MMC_SPI, 0, 0, 0);
// Enable SPI.
spi_enable(SD_MMC_SPI);
}
// Initialize SD/MMC with SPI PB clock.
sd_mmc_spi_init(spiOptions,sysclk_get_pba_hz());
#endif // SD_MMC_SPI_MEM == ENABLE
}
