static long kirin_pcie_get_resource(struct kirin_pcie *kirin_pcie, struct platform_device *pdev) { struct device *dev = &pdev->dev; struct resource *apb; struct resource *phy; struct resource *dbi; apb = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apb"); kirin_pcie->apb_base = devm_ioremap_resource(dev, apb); if (IS_ERR(kirin_pcie->apb_base)) return PTR_ERR(kirin_pcie->apb_base); phy = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy"); kirin_pcie->phy_base = devm_ioremap_resource(dev, phy); if (IS_ERR(kirin_pcie->phy_base)) return PTR_ERR(kirin_pcie->phy_base); dbi = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); kirin_pcie->pci->dbi_base = devm_ioremap_resource(dev, dbi); if (IS_ERR(kirin_pcie->pci->dbi_base)) return PTR_ERR(kirin_pcie->pci->dbi_base); kirin_pcie->crgctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3660-crgctrl"); if (IS_ERR(kirin_pcie->crgctrl)) return PTR_ERR(kirin_pcie->crgctrl); kirin_pcie->sysctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3660-sctrl"); if (IS_ERR(kirin_pcie->sysctrl)) return PTR_ERR(kirin_pcie->sysctrl); return 0; }
static int dw_mci_socfpga_parse_dt(struct dw_mci *host) { struct dw_mci_socfpga_priv_data *priv; struct device_node *np = host->dev->of_node; u32 timing[2]; u32 div = 0; int ret; priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL); if (!priv) { dev_err(host->dev, "mem alloc failed for private data\n"); return -ENOMEM; } priv->sysreg = syscon_regmap_lookup_by_compatible("altr,sys-mgr"); if (IS_ERR(priv->sysreg)) { dev_err(host->dev, "regmap for altr,sys-mgr lookup failed.\n"); return PTR_ERR(priv->sysreg); } ret = of_property_read_u32(np, "altr,dw-mshc-ciu-div", &div); if (ret) dev_info(host->dev, "No dw-mshc-ciu-div specified, assuming 1"); priv->ciu_div = div; ret = of_property_read_u32_array(np, "altr,dw-mshc-sdr-timing", timing, 2); if (ret) return ret; priv->hs_timing = SYSMGR_SDMMC_CTRL_SET(timing[0], timing[1]); host->priv = priv; return 0; }
static void __init intcp_init_early(void) { cm_map = syscon_regmap_lookup_by_compatible("arm,core-module-integrator"); if (IS_ERR(cm_map)) return; sched_clock_register(intcp_read_sched_clock, 32, 24000000); }
static void __init imx6q_1588_init(void) { struct device_node *np; struct clk *ptp_clk; struct regmap *gpr; np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-fec"); if (!np) { pr_warn("%s: failed to find fec node\n", __func__); return; } ptp_clk = of_clk_get(np, 2); if (IS_ERR(ptp_clk)) { pr_warn("%s: failed to get ptp clock\n", __func__); goto put_node; } /* * If enet_ref from ANATOP/CCM is the PTP clock source, we need to * set bit IOMUXC_GPR1[21]. Or the PTP clock must be from pad * (external OSC), and we need to clear the bit. */ gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); if (!IS_ERR(gpr)) regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_ENET_CLK_SEL_MASK, IMX6Q_GPR1_ENET_CLK_SEL_ANATOP); else pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n"); clk_put(ptp_clk); put_node: of_node_put(np); }
static void __init imx6q_usb_init(void) { struct regmap *anatop; #define HW_ANADIG_USB1_CHRG_DETECT 0x000001b0 #define HW_ANADIG_USB2_CHRG_DETECT 0x00000210 #define BM_ANADIG_USB_CHRG_DETECT_EN_B 0x00100000 #define BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B 0x00080000 anatop = syscon_regmap_lookup_by_compatible("fsl,imx6q-anatop"); if (!IS_ERR(anatop)) { /* * The external charger detector needs to be disabled, * or the signal at DP will be poor */ regmap_write(anatop, HW_ANADIG_USB1_CHRG_DETECT, BM_ANADIG_USB_CHRG_DETECT_EN_B | BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B); regmap_write(anatop, HW_ANADIG_USB2_CHRG_DETECT, BM_ANADIG_USB_CHRG_DETECT_EN_B | BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B); } else { pr_warn("failed to find fsl,imx6q-anatop regmap\n"); } }
static void __init imx6q_axi_init(void) { struct regmap *gpr; unsigned int mask; gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); if (!IS_ERR(gpr)) { /* * Enable the cacheable attribute of VPU and IPU * AXI transactions. */ mask = IMX6Q_GPR4_VPU_WR_CACHE_SEL | IMX6Q_GPR4_VPU_RD_CACHE_SEL | IMX6Q_GPR4_VPU_P_WR_CACHE_VAL | IMX6Q_GPR4_VPU_P_RD_CACHE_VAL_MASK | IMX6Q_GPR4_IPU_WR_CACHE_CTL | IMX6Q_GPR4_IPU_RD_CACHE_CTL; regmap_update_bits(gpr, IOMUXC_GPR4, mask, mask); /* Increase IPU read QoS priority */ regmap_update_bits(gpr, IOMUXC_GPR6, IMX6Q_GPR6_IPU1_ID00_RD_QOS_MASK | IMX6Q_GPR6_IPU1_ID01_RD_QOS_MASK, (0xf << 16) | (0x7 << 20)); regmap_update_bits(gpr, IOMUXC_GPR7, IMX6Q_GPR7_IPU2_ID00_RD_QOS_MASK | IMX6Q_GPR7_IPU2_ID01_RD_QOS_MASK, (0xf << 16) | (0x7 << 20)); } else { pr_warn("failed to find fsl,imx6q-iomuxc-gpr regmap\n"); } }
static void __init imx6q_csi_mux_init(void) { /* * MX6Q SabreSD board: * IPU1 CSI0 connects to parallel interface. * Set GPR1 bit 19 to 0x1. * * MX6DL SabreSD board: * IPU1 CSI0 connects to parallel interface. * Set GPR13 bit 0-2 to 0x4. * IPU1 CSI1 connects to MIPI CSI2 virtual channel 1. * Set GPR13 bit 3-5 to 0x1. */ struct regmap *gpr; gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); if (!IS_ERR(gpr)) { if (of_machine_is_compatible("fsl,imx6q-sabresd") || of_machine_is_compatible("fsl,imx6q-sabreauto")) regmap_update_bits(gpr, IOMUXC_GPR1, 1 << 19, 1 << 19); else if (of_machine_is_compatible("fsl,imx6dl-sabresd") || of_machine_is_compatible("fsl,imx6dl-sabreauto")) regmap_update_bits(gpr, IOMUXC_GPR13, 0x3F, 0x0C); } else { pr_err("%s(): failed to find fsl,imx6q-iomux-gpr regmap\n", __func__); } }
static int alt_fpga_bridge_probe(struct platform_device *pdev) { struct altera_hps2fpga_data *priv; const struct of_device_id *of_id; struct device *dev = &pdev->dev; uint32_t init_val; int rc; struct clk *clk; of_id = of_match_device(altera_fpga_of_match, dev); priv = (struct altera_hps2fpga_data *)of_id->data; WARN_ON(!priv); priv->np = dev->of_node; priv->pdev = pdev; priv->bridge_reset = devm_reset_control_get(dev, priv->name); if (IS_ERR(priv->bridge_reset)) { dev_err(dev, "Could not get %s reset control!\n", priv->name); return PTR_ERR(priv->bridge_reset); } priv->l3reg = syscon_regmap_lookup_by_compatible("altr,l3regs"); if (IS_ERR(priv->l3reg)) { dev_err(dev, "regmap for altr,l3regs lookup failed.\n"); return PTR_ERR(priv->l3reg); } clk = of_clk_get(pdev->dev.of_node, 0); if (IS_ERR(clk)) { dev_err(dev, "no clock specified\n"); return PTR_ERR(clk); } rc = clk_prepare_enable(clk); if (rc) { dev_err(dev, "could not enable clock\n"); return -EBUSY; } rc = register_fpga_bridge(pdev, &altera_hps2fpga_br_ops, priv->name, priv); if (rc) return rc; if (of_property_read_u32(priv->np, "init-val", &init_val)) dev_info(&priv->pdev->dev, "init-val not specified\n"); else if (init_val > 1) dev_warn(&priv->pdev->dev, "invalid init-val %u > 1\n", init_val); else { dev_info(&priv->pdev->dev, "%s bridge\n", (init_val ? "enabling" : "disabling")); _alt_hps2fpga_enable_set(priv, init_val); } return rc; }
void __init imx_anatop_init(void) { anatop = syscon_regmap_lookup_by_compatible("fsl,imx6q-anatop"); if (IS_ERR(anatop)) { pr_err("%s: failed to find imx6q-anatop regmap!\n", __func__); return; } }
static int alt_fpga_bridge_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct altera_hps2fpga_data *priv; const struct of_device_id *of_id; u32 enable; int ret; of_id = of_match_device(altera_fpga_of_match, dev); priv = (struct altera_hps2fpga_data *)of_id->data; priv->bridge_reset = of_reset_control_get_by_index(dev->of_node, 0); if (IS_ERR(priv->bridge_reset)) { dev_err(dev, "Could not get %s reset control\n", priv->name); return PTR_ERR(priv->bridge_reset); } if (priv->remap_mask) { priv->l3reg = syscon_regmap_lookup_by_compatible("altr,l3regs"); if (IS_ERR(priv->l3reg)) { dev_err(dev, "regmap for altr,l3regs lookup failed\n"); return PTR_ERR(priv->l3reg); } } priv->clk = devm_clk_get(dev, NULL); if (IS_ERR(priv->clk)) { dev_err(dev, "no clock specified\n"); return PTR_ERR(priv->clk); } ret = clk_prepare_enable(priv->clk); if (ret) { dev_err(dev, "could not enable clock\n"); return -EBUSY; } spin_lock_init(&l3_remap_lock); if (!of_property_read_u32(dev->of_node, "bridge-enable", &enable)) { if (enable > 1) { dev_warn(dev, "invalid bridge-enable %u > 1\n", enable); } else { dev_info(dev, "%s bridge\n", (enable ? "enabling" : "disabling")); ret = _alt_hps2fpga_enable_set(priv, enable); if (ret) { fpga_bridge_unregister(&pdev->dev); return ret; } } } return fpga_bridge_register(dev, priv->name, &altera_hps2fpga_br_ops, priv); }
static int syscon_gpio_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; const struct of_device_id *of_id; struct syscon_gpio_priv *priv; struct device_node *np = dev->of_node; int ret; of_id = of_match_device(syscon_gpio_ids, dev); if (!of_id) return -ENODEV; priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) return -ENOMEM; priv->data = of_id->data; if (priv->data->compatible) { priv->syscon = syscon_regmap_lookup_by_compatible( priv->data->compatible); if (IS_ERR(priv->syscon)) return PTR_ERR(priv->syscon); } else { priv->syscon = syscon_regmap_lookup_by_phandle(np, "gpio,syscon-dev"); if (IS_ERR(priv->syscon)) return PTR_ERR(priv->syscon); ret = of_property_read_u32_index(np, "gpio,syscon-dev", 1, &priv->dreg_offset); if (ret) dev_err(dev, "can't read the data register offset!\n"); priv->dreg_offset <<= 3; ret = of_property_read_u32_index(np, "gpio,syscon-dev", 2, &priv->dir_reg_offset); if (ret) dev_dbg(dev, "can't read the dir register offset!\n"); priv->dir_reg_offset <<= 3; } priv->chip.parent = dev; priv->chip.owner = THIS_MODULE; priv->chip.label = dev_name(dev); priv->chip.base = -1; priv->chip.ngpio = priv->data->bit_count; priv->chip.get = syscon_gpio_get; if (priv->data->flags & GPIO_SYSCON_FEAT_IN) priv->chip.direction_input = syscon_gpio_dir_in; if (priv->data->flags & GPIO_SYSCON_FEAT_OUT) { priv->chip.set = priv->data->set ? : syscon_gpio_set; priv->chip.direction_output = syscon_gpio_dir_out; }
/** * zynq_slcr_init - Regular slcr driver init * Return: 0 on success, negative errno otherwise. * * Called early during boot from platform code to remap SLCR area. */ int __init zynq_slcr_init(void) { zynq_slcr_regmap = syscon_regmap_lookup_by_compatible("xlnx,zynq-slcr"); if (IS_ERR(zynq_slcr_regmap)) { pr_err("%s: failed to find zynq-slcr\n", __func__); return -ENODEV; } return 0; }
static void __init imx6q_1588_init(void) { struct regmap *gpr; gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); if (!IS_ERR(gpr)) regmap_update_bits(gpr, 0x4, 1 << 21, 1 << 21); else pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n"); }
static void __init imx6q_enet_clk_sel(void) { struct regmap *gpr; gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); if (!IS_ERR(gpr)) regmap_update_bits(gpr, IOMUXC_GPR5, IMX6Q_GPR5_ENET_TX_CLK_SEL, IMX6Q_GPR5_ENET_TX_CLK_SEL); else pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n"); }
static int syscfg_reset_controller_register(struct device *dev, const struct syscfg_reset_controller_data *data) { struct syscfg_reset_controller *rc; size_t size; int i, err; rc = devm_kzalloc(dev, sizeof(*rc), GFP_KERNEL); if (!rc) return -ENOMEM; size = sizeof(struct syscfg_reset_channel) * data->nr_channels; rc->channels = devm_kzalloc(dev, size, GFP_KERNEL); if (!rc->channels) return -ENOMEM; rc->rst.ops = &syscfg_reset_ops, rc->rst.of_node = dev->of_node; rc->rst.nr_resets = data->nr_channels; rc->active_low = data->active_low; for (i = 0; i < data->nr_channels; i++) { struct regmap *map; struct regmap_field *f; const char *compatible = data->channels[i].compatible; map = syscon_regmap_lookup_by_compatible(compatible); if (IS_ERR(map)) return PTR_ERR(map); f = devm_regmap_field_alloc(dev, map, data->channels[i].reset); if (IS_ERR(f)) return PTR_ERR(f); rc->channels[i].reset = f; if (!data->wait_for_ack) continue; f = devm_regmap_field_alloc(dev, map, data->channels[i].ack); if (IS_ERR(f)) return PTR_ERR(f); rc->channels[i].ack = f; } err = reset_controller_register(&rc->rst); if (!err) dev_info(dev, "registered\n"); return err; }
static void __init imx7d_enet_clk_sel(void) { struct regmap *gpr; gpr = syscon_regmap_lookup_by_compatible("fsl,imx7d-iomuxc-gpr"); if (!IS_ERR(gpr)) { regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_TX_CLK_SEL_MASK, 0); regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_CLK_DIR_MASK, 0); } else { pr_err("failed to find fsl,imx7d-iomux-gpr regmap\n"); } }
static void __init imx6sl_fec_clk_init(void) { struct regmap *gpr; /* set FEC clock from internal PLL clock source */ gpr = syscon_regmap_lookup_by_compatible("fsl,imx6sl-iomuxc-gpr"); if (!IS_ERR(gpr)) { regmap_update_bits(gpr, IOMUXC_GPR1, IMX6SL_GPR1_FEC_CLOCK_MUX2_SEL_MASK, 0); regmap_update_bits(gpr, IOMUXC_GPR1, IMX6SL_GPR1_FEC_CLOCK_MUX1_SEL_MASK, 0); } else pr_err("failed to find fsl,imx6sl-iomux-gpr regmap\n"); }
static void __init imx6sx_enet_clk_sel(void) { struct regmap *gpr; gpr = syscon_regmap_lookup_by_compatible("fsl,imx6sx-iomuxc-gpr"); if (!IS_ERR(gpr)) { regmap_update_bits(gpr, IOMUXC_GPR1, IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_MASK, 0); regmap_update_bits(gpr, IOMUXC_GPR1, IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK, 0); } else { pr_err("failed to find fsl,imx6sx-iomux-gpr regmap\n"); } }
static void imx6q_fec_sleep_enable(int enabled) { struct regmap *gpr; gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); if (!IS_ERR(gpr)) { if (enabled) regmap_update_bits(gpr, IOMUXC_GPR13, IMX6Q_GPR13_ENET_STOP_REQ, IMX6Q_GPR13_ENET_STOP_REQ); else regmap_update_bits(gpr, IOMUXC_GPR13, IMX6Q_GPR13_ENET_STOP_REQ, 0); } else pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n"); }
void of_da850_pll0_init(struct device_node *node) { void __iomem *base; struct regmap *cfgchip; base = of_iomap(node, 0); if (!base) { pr_err("%s: ioremap failed\n", __func__); return; } cfgchip = syscon_regmap_lookup_by_compatible("ti,da830-cfgchip"); of_davinci_pll_init(NULL, node, &da850_pll0_info, &da850_pll0_obsclk_info, da850_pll0_sysclk_info, 7, base, cfgchip); }
static void __init rockchip_timer_init(void) { if (of_machine_is_compatible("rockchip,rk3288")) { struct regmap *grf; /* * Disable auto jtag/sdmmc switching that causes issues * with the mmc controllers making them unreliable */ grf = syscon_regmap_lookup_by_compatible("rockchip,rk3288-grf"); if (!IS_ERR(grf)) regmap_write(grf, RK3288_GRF_SOC_CON0, 0x10000000); else pr_err("rockchip: could not get grf syscon\n"); } of_clk_init(NULL); clocksource_of_init(); }
static int at91_cf_dt_init(struct platform_device *pdev) { struct at91_cf_data *board; board = devm_kzalloc(&pdev->dev, sizeof(*board), GFP_KERNEL); if (!board) return -ENOMEM; board->irq_pin = of_get_gpio(pdev->dev.of_node, 0); board->det_pin = of_get_gpio(pdev->dev.of_node, 1); board->vcc_pin = of_get_gpio(pdev->dev.of_node, 2); board->rst_pin = of_get_gpio(pdev->dev.of_node, 3); pdev->dev.platform_data = board; mc = syscon_regmap_lookup_by_compatible("atmel,at91rm9200-sdramc"); if (IS_ERR(mc)) return PTR_ERR(mc); return 0; }
/** * zynq_early_slcr_init - Early slcr init function * * Return: 0 on success, negative errno otherwise. * * Called very early during boot from platform code to unlock SLCR. */ int __init zynq_early_slcr_init(void) { struct device_node *np; np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-slcr"); if (!np) { pr_err("%s: no slcr node found\n", __func__); BUG(); } zynq_slcr_base = of_iomap(np, 0); if (!zynq_slcr_base) { pr_err("%s: Unable to map I/O memory\n", __func__); BUG(); } np->data = (__force void *)zynq_slcr_base; zynq_slcr_regmap = syscon_regmap_lookup_by_compatible("xlnx,zynq-slcr"); if (IS_ERR(zynq_slcr_regmap)) { pr_err("%s: failed to find zynq-slcr\n", __func__); return -ENODEV; } /* unlock the SLCR so that registers can be changed */ zynq_slcr_unlock(); /* See AR#54190 design advisory */ regmap_update_bits(zynq_slcr_regmap, SLCR_L2C_RAM, 0x70707, 0x20202); register_restart_handler(&zynq_slcr_restart_nb); pr_info("%s mapped to %p\n", np->name, zynq_slcr_base); of_node_put(np); return 0; }
static int lpc18xx_dwmac_probe(struct platform_device *pdev) { struct plat_stmmacenet_data *plat_dat; struct stmmac_resources stmmac_res; struct regmap *reg; u8 ethmode; int ret; ret = stmmac_get_platform_resources(pdev, &stmmac_res); if (ret) return ret; plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); if (IS_ERR(plat_dat)) return PTR_ERR(plat_dat); plat_dat->has_gmac = true; reg = syscon_regmap_lookup_by_compatible("nxp,lpc1850-creg"); if (IS_ERR(reg)) { dev_err(&pdev->dev, "syscon lookup failed\n"); return PTR_ERR(reg); } if (plat_dat->interface == PHY_INTERFACE_MODE_MII) { ethmode = LPC18XX_CREG_CREG6_ETHMODE_MII; } else if (plat_dat->interface == PHY_INTERFACE_MODE_RMII) { ethmode = LPC18XX_CREG_CREG6_ETHMODE_RMII; } else { dev_err(&pdev->dev, "Only MII and RMII mode supported\n"); return -EINVAL; } regmap_update_bits(reg, LPC18XX_CREG_CREG6, LPC18XX_CREG_CREG6_ETHMODE_MASK, ethmode); return stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); }
static void __init rockchip_timer_init(void) { if (of_machine_is_compatible("rockchip,rk3288")) { struct regmap *grf; void __iomem *reg_base; /* * Most/all uboot versions for rk3288 don't enable timer7 * which is needed for the architected timer to work. * So make sure it is running during early boot. */ reg_base = ioremap(RK3288_TIMER6_7_PHYS, SZ_16K); if (reg_base) { writel(0, reg_base + 0x30); writel(0xffffffff, reg_base + 0x20); writel(0xffffffff, reg_base + 0x24); writel(1, reg_base + 0x30); dsb(); iounmap(reg_base); } else { pr_err("rockchip: could not map timer7 registers\n"); } /* * Disable auto jtag/sdmmc switching that causes issues * with the mmc controllers making them unreliable */ grf = syscon_regmap_lookup_by_compatible("rockchip,rk3288-grf"); if (!IS_ERR(grf)) regmap_write(grf, RK3288_GRF_SOC_CON0, 0x10000000); else pr_err("rockchip: could not get grf syscon\n"); } of_clk_init(NULL); clocksource_probe(); }
static int spi_clps711x_probe(struct platform_device *pdev) { struct spi_clps711x_data *hw; struct spi_master *master; struct resource *res; int irq, ret; irq = platform_get_irq(pdev, 0); if (irq < 0) return irq; master = spi_alloc_master(&pdev->dev, sizeof(*hw)); if (!master) return -ENOMEM; master->bus_num = -1; master->mode_bits = SPI_CPHA | SPI_CS_HIGH; master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 8); master->dev.of_node = pdev->dev.of_node; master->setup = spi_clps711x_setup; master->prepare_message = spi_clps711x_prepare_message; master->transfer_one = spi_clps711x_transfer_one; hw = spi_master_get_devdata(master); hw->spi_clk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(hw->spi_clk)) { ret = PTR_ERR(hw->spi_clk); goto err_out; } hw->syscon = syscon_regmap_lookup_by_compatible("cirrus,ep7209-syscon3"); if (IS_ERR(hw->syscon)) { ret = PTR_ERR(hw->syscon); goto err_out; } res = platform_get_resource(pdev, IORESOURCE_MEM, 0); hw->syncio = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(hw->syncio)) { ret = PTR_ERR(hw->syncio); goto err_out; } /* Disable extended mode due hardware problems */ regmap_update_bits(hw->syscon, SYSCON_OFFSET, SYSCON3_ADCCON, 0); /* Clear possible pending interrupt */ readl(hw->syncio); ret = devm_request_irq(&pdev->dev, irq, spi_clps711x_isr, 0, dev_name(&pdev->dev), master); if (ret) goto err_out; ret = devm_spi_register_master(&pdev->dev, master); if (!ret) return 0; err_out: spi_master_put(master); return ret; }
static int iss_probe(struct platform_device *pdev) { struct iss_platform_data *pdata = pdev->dev.platform_data; struct iss_device *iss; unsigned int i; int ret; if (!pdata) return -EINVAL; iss = devm_kzalloc(&pdev->dev, sizeof(*iss), GFP_KERNEL); if (!iss) return -ENOMEM; mutex_init(&iss->iss_mutex); iss->dev = &pdev->dev; iss->pdata = pdata; iss->raw_dmamask = DMA_BIT_MASK(32); iss->dev->dma_mask = &iss->raw_dmamask; iss->dev->coherent_dma_mask = DMA_BIT_MASK(32); platform_set_drvdata(pdev, iss); /* * TODO: When implementing DT support switch to syscon regmap lookup by * phandle. */ iss->syscon = syscon_regmap_lookup_by_compatible("syscon"); if (IS_ERR(iss->syscon)) { ret = PTR_ERR(iss->syscon); goto error; } /* Clocks */ ret = iss_map_mem_resource(pdev, iss, OMAP4_ISS_MEM_TOP); if (ret < 0) goto error; ret = iss_get_clocks(iss); if (ret < 0) goto error; if (!omap4iss_get(iss)) goto error; ret = iss_reset(iss); if (ret < 0) goto error_iss; iss->revision = iss_reg_read(iss, OMAP4_ISS_MEM_TOP, ISS_HL_REVISION); dev_info(iss->dev, "Revision %08x found\n", iss->revision); for (i = 1; i < OMAP4_ISS_MEM_LAST; i++) { ret = iss_map_mem_resource(pdev, iss, i); if (ret) goto error_iss; } /* Configure BTE BW_LIMITER field to max recommended value (1 GB) */ iss_reg_update(iss, OMAP4_ISS_MEM_BTE, BTE_CTRL, BTE_CTRL_BW_LIMITER_MASK, 18 << BTE_CTRL_BW_LIMITER_SHIFT); /* Perform ISP reset */ ret = omap4iss_subclk_enable(iss, OMAP4_ISS_SUBCLK_ISP); if (ret < 0) goto error_iss; ret = iss_isp_reset(iss); if (ret < 0) goto error_iss; dev_info(iss->dev, "ISP Revision %08x found\n", iss_reg_read(iss, OMAP4_ISS_MEM_ISP_SYS1, ISP5_REVISION)); /* Interrupt */ ret = platform_get_irq(pdev, 0); if (ret <= 0) { dev_err(iss->dev, "No IRQ resource\n"); ret = -ENODEV; goto error_iss; } iss->irq_num = ret; if (devm_request_irq(iss->dev, iss->irq_num, iss_isr, IRQF_SHARED, "OMAP4 ISS", iss)) { dev_err(iss->dev, "Unable to request IRQ\n"); ret = -EINVAL; goto error_iss; } /* Entities */ ret = iss_initialize_modules(iss); if (ret < 0) goto error_iss; ret = iss_register_entities(iss); if (ret < 0) goto error_modules; ret = media_entity_enum_init(&iss->crashed, &iss->media_dev); if (ret) goto error_entities; ret = iss_create_links(iss); if (ret < 0) goto error_entities; omap4iss_put(iss); return 0; error_entities: iss_unregister_entities(iss); media_entity_enum_cleanup(&iss->crashed); error_modules: iss_cleanup_modules(iss); error_iss: omap4iss_put(iss); error: platform_set_drvdata(pdev, NULL); mutex_destroy(&iss->iss_mutex); return ret; }
static int imx6q_sata_init(struct device *dev, void __iomem *mmio) { int ret = 0; unsigned int reg_val; struct imx_ahci_priv *imxpriv = dev_get_drvdata(dev->parent); imxpriv->gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); if (IS_ERR(imxpriv->gpr)) { dev_err(dev, "failed to find fsl,imx6q-iomux-gpr regmap\n"); return PTR_ERR(imxpriv->gpr); } ret = clk_prepare_enable(imxpriv->sata_ref_clk); if (ret < 0) { dev_err(dev, "prepare-enable sata_ref clock err:%d\n", ret); return ret; } /* * set PHY Paremeters, two steps to configure the GPR13, * one write for rest of parameters, mask of first write * is 0x07fffffd, and the other one write for setting * the mpll_clk_en. */ regmap_update_bits(imxpriv->gpr, 0x34, IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK | IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK | IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK | IMX6Q_GPR13_SATA_SPD_MODE_MASK | IMX6Q_GPR13_SATA_MPLL_SS_EN | IMX6Q_GPR13_SATA_TX_ATTEN_MASK | IMX6Q_GPR13_SATA_TX_BOOST_MASK | IMX6Q_GPR13_SATA_TX_LVL_MASK | IMX6Q_GPR13_SATA_TX_EDGE_RATE , IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB | IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M | IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F | IMX6Q_GPR13_SATA_SPD_MODE_3P0G | IMX6Q_GPR13_SATA_MPLL_SS_EN | IMX6Q_GPR13_SATA_TX_ATTEN_9_16 | IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB | IMX6Q_GPR13_SATA_TX_LVL_1_025_V); regmap_update_bits(imxpriv->gpr, 0x34, IMX6Q_GPR13_SATA_MPLL_CLK_EN, IMX6Q_GPR13_SATA_MPLL_CLK_EN); usleep_range(100, 200); /* * Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL, * and IP vendor specific register HOST_TIMER1MS. * Configure CAP_SSS (support stagered spin up). * Implement the port0. * Get the ahb clock rate, and configure the TIMER1MS register. */ reg_val = readl(mmio + HOST_CAP); if (!(reg_val & HOST_CAP_SSS)) { reg_val |= HOST_CAP_SSS; writel(reg_val, mmio + HOST_CAP); } reg_val = readl(mmio + HOST_PORTS_IMPL); if (!(reg_val & 0x1)) { reg_val |= 0x1; writel(reg_val, mmio + HOST_PORTS_IMPL); } reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000; writel(reg_val, mmio + HOST_TIMER1MS); return 0; }
static int __init meson_mx_socinfo_init(void) { struct soc_device_attribute *soc_dev_attr; struct soc_device *soc_dev; struct device_node *np; struct regmap *assist_regmap, *bootrom_regmap, *analog_top_regmap; unsigned int major_ver, misc_ver, metal_rev = 0; int ret; assist_regmap = syscon_regmap_lookup_by_compatible("amlogic,meson-mx-assist"); if (IS_ERR(assist_regmap)) return PTR_ERR(assist_regmap); bootrom_regmap = syscon_regmap_lookup_by_compatible("amlogic,meson-mx-bootrom"); if (IS_ERR(bootrom_regmap)) return PTR_ERR(bootrom_regmap); np = of_find_matching_node(NULL, meson_mx_socinfo_analog_top_ids); if (np) { analog_top_regmap = syscon_node_to_regmap(np); if (IS_ERR(analog_top_regmap)) return PTR_ERR(analog_top_regmap); ret = regmap_read(analog_top_regmap, MESON_MX_ANALOG_TOP_METAL_REVISION, &metal_rev); if (ret) return ret; } ret = regmap_read(assist_regmap, MESON_MX_ASSIST_HW_REV, &major_ver); if (ret < 0) return ret; ret = regmap_read(bootrom_regmap, MESON_MX_BOOTROM_MISC_VER, &misc_ver); if (ret < 0) return ret; soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); if (!soc_dev_attr) return -ENODEV; soc_dev_attr->family = "Amlogic Meson"; np = of_find_node_by_path("/"); of_property_read_string(np, "model", &soc_dev_attr->machine); of_node_put(np); soc_dev_attr->revision = meson_mx_socinfo_revision(major_ver, misc_ver, metal_rev); soc_dev_attr->soc_id = meson_mx_socinfo_soc_id(major_ver, metal_rev); soc_dev = soc_device_register(soc_dev_attr); if (IS_ERR(soc_dev)) { kfree_const(soc_dev_attr->revision); kfree_const(soc_dev_attr->soc_id); kfree(soc_dev_attr); return PTR_ERR(soc_dev); } dev_info(soc_device_to_device(soc_dev), "Amlogic %s %s detected\n", soc_dev_attr->soc_id, soc_dev_attr->revision); return 0; }
static int da8xx_usb_phy_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct device_node *node = dev->of_node; struct da8xx_usb_phy *d_phy; d_phy = devm_kzalloc(dev, sizeof(*d_phy), GFP_KERNEL); if (!d_phy) return -ENOMEM; if (node) d_phy->regmap = syscon_regmap_lookup_by_compatible( "ti,da830-cfgchip"); else d_phy->regmap = syscon_regmap_lookup_by_pdevname("syscon.0"); if (IS_ERR(d_phy->regmap)) { dev_err(dev, "Failed to get syscon\n"); return PTR_ERR(d_phy->regmap); } d_phy->usb11_clk = devm_clk_get(dev, "usb11_phy"); if (IS_ERR(d_phy->usb11_clk)) { dev_err(dev, "Failed to get usb11_phy clock\n"); return PTR_ERR(d_phy->usb11_clk); } d_phy->usb20_clk = devm_clk_get(dev, "usb20_phy"); if (IS_ERR(d_phy->usb20_clk)) { dev_err(dev, "Failed to get usb20_phy clock\n"); return PTR_ERR(d_phy->usb20_clk); } d_phy->usb11_phy = devm_phy_create(dev, node, &da8xx_usb11_phy_ops); if (IS_ERR(d_phy->usb11_phy)) { dev_err(dev, "Failed to create usb11 phy\n"); return PTR_ERR(d_phy->usb11_phy); } d_phy->usb20_phy = devm_phy_create(dev, node, &da8xx_usb20_phy_ops); if (IS_ERR(d_phy->usb20_phy)) { dev_err(dev, "Failed to create usb20 phy\n"); return PTR_ERR(d_phy->usb20_phy); } platform_set_drvdata(pdev, d_phy); phy_set_drvdata(d_phy->usb11_phy, d_phy); phy_set_drvdata(d_phy->usb20_phy, d_phy); if (node) { d_phy->phy_provider = devm_of_phy_provider_register(dev, da8xx_usb_phy_of_xlate); if (IS_ERR(d_phy->phy_provider)) { dev_err(dev, "Failed to create phy provider\n"); return PTR_ERR(d_phy->phy_provider); } } else { int ret; ret = phy_create_lookup(d_phy->usb11_phy, "usb-phy", "ohci.0"); if (ret) dev_warn(dev, "Failed to create usb11 phy lookup\n"); ret = phy_create_lookup(d_phy->usb20_phy, "usb-phy", "musb-da8xx"); if (ret) dev_warn(dev, "Failed to create usb20 phy lookup\n"); } return 0; }