static int arm11_assert_reset(struct target *target)
{
struct arm11_common *arm11 = target_to_arm11(target);
/* optionally catch reset vector */
if (target->reset_halt && !(arm11->vcr & 1))
CHECK_RETVAL(arm11_sc7_set_vcr(arm11, arm11->vcr | 1));
/* Issue some kind of warm reset. */
if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
} else if (jtag_get_reset_config() & RESET_HAS_SRST) {
/* REVISIT handle "pulls" cases, if there's
* hardware that needs them to work.
*/
jtag_add_reset(0, 1);
} else {
LOG_ERROR("%s: how to reset?", target_name(target));
return ERROR_FAIL;
}
/* registers are now invalid */
register_cache_invalidate(arm11->arm.core_cache);
target->state = TARGET_RESET;
return ERROR_OK;
}
static int arm11_deassert_reset(struct target *target)
{
struct arm11_common *arm11 = target_to_arm11(target);
int retval;
/* be certain SRST is off */
jtag_add_reset(0, 0);
/* WORKAROUND i.MX31 problems: SRST goofs the TAP, and resets
* at least DSCR. OMAP24xx doesn't show that problem, though
* SRST-only reset seems to be problematic for other reasons.
* (Secure boot sequences being one likelihood!)
*/
jtag_add_tlr();
CHECK_RETVAL(arm11_poll(target));
if (target->reset_halt) {
if (target->state != TARGET_HALTED) {
LOG_WARNING("%s: ran after reset and before halt ...",
target_name(target));
if ((retval = target_halt(target)) != ERROR_OK)
return retval;
}
}
/* maybe restore vector catch config */
if (target->reset_halt && !(arm11->vcr & 1))
CHECK_RETVAL(arm11_sc7_set_vcr(arm11, arm11->vcr));
return ERROR_OK;
}
/* target break-/watchpoint control
* rw: 0 = write, 1 = read, 2 = access
*/
static int arm11_add_breakpoint(struct target *target,
struct breakpoint *breakpoint)
{
struct arm11_common *arm11 = target_to_arm11(target);
#if 0
if (breakpoint->type == BKPT_SOFT)
{
LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
#endif
if (!arm11->free_brps)
{
LOG_DEBUG("no breakpoint unit available for hardware breakpoint");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
if (breakpoint->length != 4)
{
LOG_DEBUG("only breakpoints of four bytes length supported");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
arm11->free_brps--;
return ERROR_OK;
}
/* poll current target status */
static int arm11_poll(struct target *target)
{
int retval;
struct arm11_common *arm11 = target_to_arm11(target);
CHECK_RETVAL(arm11_check_init(arm11));
if (arm11->dscr & DSCR_CORE_HALTED) {
if (target->state != TARGET_HALTED) {
enum target_state old_state = target->state;
LOG_DEBUG("enter TARGET_HALTED");
retval = arm11_debug_entry(arm11);
if (retval != ERROR_OK)
return retval;
target_call_event_callbacks(target,
(old_state == TARGET_DEBUG_RUNNING)
? TARGET_EVENT_DEBUG_HALTED
: TARGET_EVENT_HALTED);
}
} else {
if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING) {
LOG_DEBUG("enter TARGET_RUNNING");
target->state = TARGET_RUNNING;
target->debug_reason = DBG_REASON_NOTHALTED;
}
}
return ERROR_OK;
}
/* target execution control */
static int arm11_halt(struct target *target)
{
struct arm11_common *arm11 = target_to_arm11(target);
LOG_DEBUG("target->state: %s",
target_state_name(target));
if (target->state == TARGET_UNKNOWN)
{
arm11->simulate_reset_on_next_halt = true;
}
if (target->state == TARGET_HALTED)
{
LOG_DEBUG("target was already halted");
return ERROR_OK;
}
arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);
CHECK_RETVAL(jtag_execute_queue());
int i = 0;
while (1)
{
CHECK_RETVAL(arm11_read_DSCR(arm11));
if (arm11->dscr & DSCR_CORE_HALTED)
break;
long long then = 0;
if (i == 1000)
{
then = timeval_ms();
}
if (i >= 1000)
{
if ((timeval_ms()-then) > 1000)
{
LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
return ERROR_FAIL;
}
}
i++;
}
enum target_state old_state = target->state;
CHECK_RETVAL(arm11_debug_entry(arm11));
CHECK_RETVAL(
target_call_event_callbacks(target,
old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED));
return ERROR_OK;
}
static int arm11_remove_breakpoint(struct target *target,
struct breakpoint *breakpoint)
{
struct arm11_common *arm11 = target_to_arm11(target);
arm11->free_brps++;
return ERROR_OK;
}
/* architecture specific status reply */
static int arm11_arch_state(struct target *target)
{
struct arm11_common *arm11 = target_to_arm11(target);
int retval;
retval = arm_arch_state(target);
/* REVISIT also display ARM11-specific MMU and cache status ... */
if (target->debug_reason == DBG_REASON_WATCHPOINT)
LOG_USER("Watchpoint triggered at PC %#08x",
(unsigned) arm11->dpm.wp_pc);
return retval;
}
static int arm11_assert_reset(struct target *target)
{
struct arm11_common *arm11 = target_to_arm11(target);
if (!(target_was_examined(target))) {
if (jtag_get_reset_config() & RESET_HAS_SRST)
jtag_add_reset(0, 1);
else {
LOG_WARNING("Reset is not asserted because the target is not examined.");
LOG_WARNING("Use a reset button or power cycle the target.");
return ERROR_TARGET_NOT_EXAMINED;
}
} else {
/* optionally catch reset vector */
if (target->reset_halt && !(arm11->vcr & 1))
CHECK_RETVAL(arm11_sc7_set_vcr(arm11, arm11->vcr | 1));
/* Issue some kind of warm reset. */
if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT))
target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
else if (jtag_get_reset_config() & RESET_HAS_SRST) {
/* REVISIT handle "pulls" cases, if there's
* hardware that needs them to work.
*/
jtag_add_reset(0, 1);
} else {
LOG_ERROR("%s: how to reset?", target_name(target));
return ERROR_FAIL;
}
}
/* registers are now invalid */
register_cache_invalidate(arm11->arm.core_cache);
target->state = TARGET_RESET;
return ERROR_OK;
}
/*
* no_increment - in the future we may want to be able
* to read/write a range of data to a "port". a "port" is an action on
* read memory address for some peripheral.
*/
static int arm11_write_memory_inner(struct target *target,
uint32_t address, uint32_t size,
uint32_t count, const uint8_t *buffer,
bool no_increment)
{
int retval;
if (target->state != TARGET_HALTED)
{
LOG_WARNING("target was not halted");
return ERROR_TARGET_NOT_HALTED;
}
LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count);
struct arm11_common *arm11 = target_to_arm11(target);
retval = arm11_run_instr_data_prepare(arm11);
if (retval != ERROR_OK)
return retval;
/* load r0 with buffer address */
/* MRC p14,0,r0,c0,c5,0 */
retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
if (retval != ERROR_OK)
return retval;
/* burst writes are not used for single words as those may well be
* reset init script writes.
*
* The other advantage is that as burst writes are default, we'll
* now exercise both burst and non-burst code paths with the
* default settings, increasing code coverage.
*/
bool burst = arm11->memwrite_burst && (count > 1);
switch (size)
{
case 1:
{
arm11->arm.core_cache->reg_list[1].dirty = true;
for (size_t i = 0; i < count; i++)
{
/* load r1 from DCC with byte data */
/* MRC p14,0,r1,c0,c5,0 */
retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
if (retval != ERROR_OK)
return retval;
/* write r1 to memory */
/* strb r1, [r0], #1 */
/* strb r1, [r0] */
retval = arm11_run_instr_no_data1(arm11,
!no_increment
? 0xe4c01001
: 0xe5c01000);
if (retval != ERROR_OK)
return retval;
}
break;
}
case 2:
{
arm11->arm.core_cache->reg_list[1].dirty = true;
for (size_t i = 0; i < count; i++)
{
uint16_t value;
memcpy(&value, buffer + i * sizeof(uint16_t), sizeof(uint16_t));
/* load r1 from DCC with halfword data */
/* MRC p14,0,r1,c0,c5,0 */
retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, value);
if (retval != ERROR_OK)
return retval;
/* write r1 to memory */
/* strh r1, [r0], #2 */
/* strh r1, [r0] */
retval = arm11_run_instr_no_data1(arm11,
!no_increment
? 0xe0c010b2
: 0xe1c010b0);
if (retval != ERROR_OK)
return retval;
}
break;
}
case 4: {
/* stream word data through DCC directly to memory */
/* increment: STC p14,c5,[R0],#4 */
/* no increment: STC p14,c5,[R0]*/
uint32_t instr = !no_increment ? 0xeca05e01 : 0xed805e00;
/** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
uint32_t *words = (uint32_t*)(void *)buffer;
/* "burst" here just means trusting each instruction executes
* fully before we run the next one: per-word roundtrips, to
* check the Ready flag, are not used.
*/
if (!burst)
retval = arm11_run_instr_data_to_core(arm11,
instr, words, count);
else
retval = arm11_run_instr_data_to_core_noack(arm11,
instr, words, count);
if (retval != ERROR_OK)
return retval;
break;
}
}
/* r0 verification */
if (!no_increment)
{
uint32_t r0;
/* MCR p14,0,R0,c0,c5,0 */
retval = arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
if (retval != ERROR_OK)
return retval;
if (address + size * count != r0)
{
LOG_ERROR("Data transfer failed. Expected end "
"address 0x%08x, got 0x%08x",
(unsigned) (address + size * count),
(unsigned) r0);
if (burst)
LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
if (arm11->memwrite_error_fatal)
return ERROR_FAIL;
}
}
return arm11_run_instr_data_finish(arm11);
}
/* target memory access
* size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
* count: number of items of <size>
*
* arm11_config_memrw_no_increment - in the future we may want to be able
* to read/write a range of data to a "port". a "port" is an action on
* read memory address for some peripheral.
*/
static int arm11_read_memory_inner(struct target *target,
uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer,
bool arm11_config_memrw_no_increment)
{
/** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */
int retval;
if (target->state != TARGET_HALTED)
{
LOG_WARNING("target was not halted");
return ERROR_TARGET_NOT_HALTED;
}
LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count);
struct arm11_common *arm11 = target_to_arm11(target);
retval = arm11_run_instr_data_prepare(arm11);
if (retval != ERROR_OK)
return retval;
/* MRC p14,0,r0,c0,c5,0 */
retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
if (retval != ERROR_OK)
return retval;
switch (size)
{
case 1:
arm11->arm.core_cache->reg_list[1].dirty = true;
for (size_t i = 0; i < count; i++)
{
/* ldrb r1, [r0], #1 */
/* ldrb r1, [r0] */
CHECK_RETVAL(arm11_run_instr_no_data1(arm11,
!arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000));
uint32_t res;
/* MCR p14,0,R1,c0,c5,0 */
CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1));
*buffer++ = res;
}
break;
case 2:
{
arm11->arm.core_cache->reg_list[1].dirty = true;
for (size_t i = 0; i < count; i++)
{
/* ldrh r1, [r0], #2 */
CHECK_RETVAL(arm11_run_instr_no_data1(arm11,
!arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0));
uint32_t res;
/* MCR p14,0,R1,c0,c5,0 */
CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1));
uint16_t svalue = res;
memcpy(buffer + i * sizeof(uint16_t), &svalue, sizeof(uint16_t));
}
break;
}
case 4:
{
uint32_t instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00;
/** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
uint32_t *words = (uint32_t *)(void *)buffer;
/* LDC p14,c5,[R0],#4 */
/* LDC p14,c5,[R0] */
CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, instr, words, count));
break;
}
}
return arm11_run_instr_data_finish(arm11);
}
static int arm11_step(struct target *target, int current,
uint32_t address, int handle_breakpoints)
{
LOG_DEBUG("target->state: %s",
target_state_name(target));
if (target->state != TARGET_HALTED)
{
LOG_WARNING("target was not halted");
return ERROR_TARGET_NOT_HALTED;
}
struct arm11_common *arm11 = target_to_arm11(target);
address = arm11_nextpc(arm11, current, address);
LOG_DEBUG("STEP PC %08" PRIx32 "%s", address, !current ? "!" : "");
/** \todo TODO: Thumb not supported here */
uint32_t next_instruction;
CHECK_RETVAL(arm11_read_memory_word(arm11, address, &next_instruction));
/* skip over BKPT */
if ((next_instruction & 0xFFF00070) == 0xe1200070)
{
address = arm11_nextpc(arm11, 0, address + 4);
LOG_DEBUG("Skipping BKPT");
}
/* skip over Wait for interrupt / Standby */
/* mcr 15, 0, r?, cr7, cr0, {4} */
else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
{
address = arm11_nextpc(arm11, 0, address + 4);
LOG_DEBUG("Skipping WFI");
}
/* ignore B to self */
else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
{
LOG_DEBUG("Not stepping jump to self");
}
else
{
/** \todo TODO: check if break-/watchpoints make any sense at all in combination
* with this. */
/** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
* the VCR might be something worth looking into. */
/* Set up breakpoint for stepping */
struct arm11_sc7_action brp[2];
brp[0].write = 1;
brp[0].address = ARM11_SC7_BVR0;
brp[1].write = 1;
brp[1].address = ARM11_SC7_BCR0;
if (arm11->hardware_step)
{
/* Hardware single stepping ("instruction address
* mismatch") is used if enabled. It's not quite
* exactly "run one instruction"; "branch to here"
* loops won't break, neither will some other cases,
* but it's probably the best default.
*
* Hardware single stepping isn't supported on v6
* debug modules. ARM1176 and v7 can support it...
*
* FIXME Thumb stepping likely needs to use 0x03
* or 0xc0 byte masks, not 0x0f.
*/
brp[0].value = address;
brp[1].value = 0x1 | (3 << 1) | (0x0F << 5)
| (0 << 14) | (0 << 16) | (0 << 20)
| (2 << 21);
} else
{
/* Sets a breakpoint on the next PC, as calculated
* by instruction set simulation.
*
* REVISIT stepping Thumb on ARM1156 requires Thumb2
* support from the simulator.
*/
uint32_t next_pc;
int retval;
retval = arm_simulate_step(target, &next_pc);
if (retval != ERROR_OK)
return retval;
brp[0].value = next_pc;
brp[1].value = 0x1 | (3 << 1) | (0x0F << 5)
| (0 << 14) | (0 << 16) | (0 << 20)
| (0 << 21);
}
CHECK_RETVAL(arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp)));
/* resume */
if (arm11->step_irq_enable)
/* this disable should be redundant ... */
arm11->dscr &= ~DSCR_INT_DIS;
else
arm11->dscr |= DSCR_INT_DIS;
CHECK_RETVAL(arm11_leave_debug_state(arm11, handle_breakpoints));
arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
CHECK_RETVAL(jtag_execute_queue());
/* wait for halt */
int i = 0;
while (1)
{
const uint32_t mask = DSCR_CORE_RESTARTED
| DSCR_CORE_HALTED;
CHECK_RETVAL(arm11_read_DSCR(arm11));
LOG_DEBUG("DSCR %08x e", (unsigned) arm11->dscr);
if ((arm11->dscr & mask) == mask)
break;
long long then = 0;
if (i == 1000)
{
then = timeval_ms();
}
if (i >= 1000)
{
if ((timeval_ms()-then) > 1000)
{
LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
return ERROR_FAIL;
}
}
i++;
}
/* clear breakpoint */
CHECK_RETVAL(arm11_sc7_clear_vbw(arm11));
/* save state */
CHECK_RETVAL(arm11_debug_entry(arm11));
/* restore default state */
arm11->dscr &= ~DSCR_INT_DIS;
}
target->debug_reason = DBG_REASON_SINGLESTEP;
CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
return ERROR_OK;
}
static int arm11_resume(struct target *target, int current,
uint32_t address, int handle_breakpoints, int debug_execution)
{
// LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
// current, address, handle_breakpoints, debug_execution);
struct arm11_common *arm11 = target_to_arm11(target);
LOG_DEBUG("target->state: %s",
target_state_name(target));
if (target->state != TARGET_HALTED)
{
LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
address = arm11_nextpc(arm11, current, address);
LOG_DEBUG("RESUME PC %08" PRIx32 "%s", address, !current ? "!" : "");
/* clear breakpoints/watchpoints and VCR*/
CHECK_RETVAL(arm11_sc7_clear_vbw(arm11));
if (!debug_execution)
target_free_all_working_areas(target);
/* Should we skip over breakpoints matching the PC? */
if (handle_breakpoints) {
struct breakpoint *bp;
for (bp = target->breakpoints; bp; bp = bp->next)
{
if (bp->address == address)
{
LOG_DEBUG("must step over %08" PRIx32 "", bp->address);
arm11_step(target, 1, 0, 0);
break;
}
}
}
/* activate all breakpoints */
if (true) {
struct breakpoint *bp;
unsigned brp_num = 0;
for (bp = target->breakpoints; bp; bp = bp->next)
{
struct arm11_sc7_action brp[2];
brp[0].write = 1;
brp[0].address = ARM11_SC7_BVR0 + brp_num;
brp[0].value = bp->address;
brp[1].write = 1;
brp[1].address = ARM11_SC7_BCR0 + brp_num;
brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
CHECK_RETVAL(arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp)));
LOG_DEBUG("Add BP %d at %08" PRIx32, brp_num,
bp->address);
brp_num++;
}
if (arm11->vcr)
CHECK_RETVAL(arm11_sc7_set_vcr(arm11, arm11->vcr));
}
/* activate all watchpoints and breakpoints */
CHECK_RETVAL(arm11_leave_debug_state(arm11, true));
arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
CHECK_RETVAL(jtag_execute_queue());
int i = 0;
while (1)
{
CHECK_RETVAL(arm11_read_DSCR(arm11));
LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr);
if (arm11->dscr & DSCR_CORE_RESTARTED)
break;
long long then = 0;
if (i == 1000)
{
then = timeval_ms();
}
if (i >= 1000)
{
if ((timeval_ms()-then) > 1000)
{
LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
return ERROR_FAIL;
}
}
i++;
}
target->debug_reason = DBG_REASON_NOTHALTED;
if (!debug_execution)
target->state = TARGET_RUNNING;
else
target->state = TARGET_DEBUG_RUNNING;
CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
return ERROR_OK;
}
/* talk to the target and set things up */
static int arm11_examine(struct target *target)
{
int retval;
char *type;
struct arm11_common *arm11 = target_to_arm11(target);
uint32_t didr, device_id;
uint8_t implementor;
/* FIXME split into do-first-time and do-every-time logic ... */
/* check IDCODE */
arm11_add_IR(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT);
struct scan_field idcode_field;
arm11_setup_field(arm11, 32, NULL, &device_id, &idcode_field);
arm11_add_dr_scan_vc(arm11->arm.target->tap, 1, &idcode_field, TAP_DRPAUSE);
/* check DIDR */
arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
struct scan_field chain0_fields[2];
arm11_setup_field(arm11, 32, NULL, &didr, chain0_fields + 0);
arm11_setup_field(arm11, 8, NULL, &implementor, chain0_fields + 1);
arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(chain0_fields), chain0_fields, TAP_IDLE);
CHECK_RETVAL(jtag_execute_queue());
/* assume the manufacturer id is ok; check the part # */
switch ((device_id >> 12) & 0xFFFF)
{
case 0x7B36:
type = "ARM1136";
break;
case 0x7B37:
type = "ARM11 MPCore";
break;
case 0x7B56:
type = "ARM1156";
break;
case 0x7B76:
arm11->arm.core_type = ARM_MODE_MON;
/* NOTE: could default arm11->hardware_step to true */
type = "ARM1176";
break;
default:
LOG_ERROR("unexpected ARM11 ID code");
return ERROR_FAIL;
}
LOG_INFO("found %s", type);
/* unlikely this could ever fail, but ... */
switch ((didr >> 16) & 0x0F) {
case ARM11_DEBUG_V6:
case ARM11_DEBUG_V61: /* supports security extensions */
break;
default:
LOG_ERROR("Only ARM v6 and v6.1 debug supported.");
return ERROR_FAIL;
}
arm11->brp = ((didr >> 24) & 0x0F) + 1;
/** \todo TODO: reserve one brp slot if we allow breakpoints during step */
arm11->free_brps = arm11->brp;
LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32,
device_id, implementor, didr);
/* as a side-effect this reads DSCR and thus
* clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
* as suggested by the spec.
*/
retval = arm11_check_init(arm11);
if (retval != ERROR_OK)
return retval;
/* Build register cache "late", after target_init(), since we
* want to know if this core supports Secure Monitor mode.
*/
if (!target_was_examined(target))
CHECK_RETVAL(arm11_dpm_init(arm11, didr));
/* ETM on ARM11 still uses original scanchain 6 access mode */
if (arm11->arm.etm && !target_was_examined(target)) {
*register_get_last_cache_p(&target->reg_cache) =
etm_build_reg_cache(target, &arm11->jtag_info,
arm11->arm.etm);
CHECK_RETVAL(etm_setup(target));
}
target_set_examined(target);
return ERROR_OK;
}