static int tegra_camera_enable_clk(struct tegra_camera_dev *dev)
{
#ifdef CONFIG_VIDEO_OV5640
printk("%s++\n", __func__);
#endif
clk_enable(dev->vi_clk);
clk_enable(dev->vi_sensor_clk);
clk_enable(dev->csus_clk);
tegra_periph_reset_assert(dev->vi_clk);
udelay(2);
tegra_periph_reset_deassert(dev->vi_clk);
clk_enable(dev->isp_clk);
tegra_periph_reset_assert(dev->isp_clk);
udelay(2);
tegra_periph_reset_deassert(dev->isp_clk);
clk_enable(dev->csi_clk);
tegra_periph_reset_assert(dev->csi_clk);
udelay(2);
tegra_periph_reset_deassert(dev->csi_clk);
#ifdef CONFIG_VIDEO_OV5640
printk("%s--\n", __func__);
#endif
return 0;
}
/* Must be called with clk disabled, and returns with clk enabled */
int tegra_powergate_sequence_power_up(int id, struct clk *clk)
{
int ret;
tegra_periph_reset_assert(clk);
ret = tegra_powergate_power_on(id);
if (ret)
goto err_power;
ret = clk_prepare_enable(clk);
if (ret)
goto err_clk;
udelay(10);
ret = tegra_powergate_remove_clamping(id);
if (ret)
goto err_clamp;
udelay(10);
tegra_periph_reset_deassert(clk);
return 0;
err_clamp:
clk_disable_unprepare(clk);
err_clk:
tegra_powergate_power_off(id);
err_power:
return ret;
}
static bool _tegra_dc_enable(struct tegra_dc *dc)
{
if (dc->mode.pclk == 0)
return false;
tegra_dc_io_start(dc);
if (dc->out && dc->out->enable)
dc->out->enable();
tegra_dc_setup_clk(dc, dc->clk);
clk_enable(dc->clk);
clk_enable(dc->emc_clk);
tegra_periph_reset_deassert(dc->clk);
msleep(10);
enable_irq(dc->irq);
tegra_dc_init(dc);
if (dc->out_ops && dc->out_ops->enable)
dc->out_ops->enable(dc);
/* force a full blending update */
dc->blend.z[0] = -1;
tegra_dc_ext_enable(dc->ext);
return true;
}
static int tegra_mipi_bif_init(struct tegra_mipi_bif_dev *mipi_bif_dev)
{
u32 fifo_control;
pm_runtime_get_sync(mipi_bif_dev->dev);
clk_prepare_enable(mipi_bif_dev->mipi_bif_clk);
tegra_periph_reset_assert(mipi_bif_dev->mipi_bif_clk);
udelay(2);
tegra_periph_reset_deassert(mipi_bif_dev->mipi_bif_clk);
clk_set_rate(mipi_bif_dev->mipi_bif_clk,
mipi_bif_dev->bus_clk_rate * 1000000);
writel(0, mipi_bif_dev->base + MIPIBIF_INTERRUPT_EN);
fifo_control = 0 << MIPIBIF_RXFIFO_ATN_LVL_SHIFT;
fifo_control |= 5 << MIPIBIF_TXFIFO_ATN_LVL_SHIFT;
fifo_control |= MIPIBIF_RXFIFO_FLUSH;
fifo_control |= MIPIBIF_TXFIFO_FLUSH;
writel(fifo_control, mipi_bif_dev->base + MIPIBIF_FIFO_CONTROL);
tegra_mipi_bif_program_timings(mipi_bif_dev);
clk_disable_unprepare(mipi_bif_dev->mipi_bif_clk);
pm_runtime_put(mipi_bif_dev->dev);
return 0;
}
static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
{
bool ret = true;
if (dc->out->enable)
dc->out->enable();
tegra_dc_setup_clk(dc, dc->clk);
tegra_dc_clk_enable(dc);
if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
mutex_lock(&tegra_dcs[1]->lock);
disable_irq(tegra_dcs[1]->irq);
} else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
mutex_lock(&tegra_dcs[0]->lock);
disable_irq(tegra_dcs[0]->irq);
}
msleep(5);
tegra_periph_reset_assert(dc->clk);
msleep(2);
#ifdef CONFIG_TEGRA_SILICON_PLATFORM
tegra_periph_reset_deassert(dc->clk);
msleep(1);
#endif
if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
enable_dc_irq(tegra_dcs[1]->irq);
mutex_unlock(&tegra_dcs[1]->lock);
} else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
enable_dc_irq(tegra_dcs[0]->irq);
mutex_unlock(&tegra_dcs[0]->lock);
}
enable_dc_irq(dc->irq);
if (tegra_dc_init(dc)) {
dev_err(&dc->ndev->dev, "cannot initialize\n");
ret = false;
}
if (dc->out_ops && dc->out_ops->enable)
dc->out_ops->enable(dc);
if (dc->out->postpoweron)
dc->out->postpoweron();
/* force a full blending update */
dc->blend.z[0] = -1;
tegra_dc_ext_enable(dc->ext);
if (!ret) {
dev_err(&dc->ndev->dev, "initialization failed,disabling");
_tegra_dc_controller_disable(dc);
}
trace_printk("%s:reset enable\n", dc->ndev->name);
return ret;
}
static void bpmp_reset(u32 addr)
{
bpmp_stop();
writel(addr, TEGRA_NVAVP_RESET_VECTOR_ADDR);
tegra_periph_reset_assert(cop_clk);
udelay(2);
tegra_periph_reset_deassert(cop_clk);
writel(FLOW_MODE_NONE, FLOW_CTRL_HALT_COP_EVENTS);
}
static int tegra_camera_enable_clk(struct tegra_camera_dev *dev)
{
clk_enable(dev->vi_clk);
clk_enable(dev->vi_sensor_clk);
clk_enable(dev->csus_clk);
tegra_periph_reset_assert(dev->vi_clk);
udelay(2);
tegra_periph_reset_deassert(dev->vi_clk);
clk_enable(dev->isp_clk);
tegra_periph_reset_assert(dev->isp_clk);
udelay(2);
tegra_periph_reset_deassert(dev->isp_clk);
clk_enable(dev->csi_clk);
tegra_periph_reset_assert(dev->csi_clk);
udelay(2);
tegra_periph_reset_deassert(dev->csi_clk);
return 0;
}
void nvhost_module_reset(struct device *dev, struct nvhost_module *mod)
{
dev_dbg(dev,
"%s: asserting %s module reset (id %d, id2 %d)\n",
__func__, mod->name,
mod->desc->powergate_ids[0], mod->desc->powergate_ids[1]);
/* assert module and mc client reset */
if (mod->desc->powergate_ids[0] != -1) {
tegra_powergate_mc_disable(mod->desc->powergate_ids[0]);
tegra_periph_reset_assert(mod->clk[0]);
tegra_powergate_mc_flush(mod->desc->powergate_ids[0]);
}
if (mod->desc->powergate_ids[1] != -1) {
tegra_powergate_mc_disable(mod->desc->powergate_ids[1]);
tegra_periph_reset_assert(mod->clk[1]);
tegra_powergate_mc_flush(mod->desc->powergate_ids[1]);
}
udelay(POWERGATE_DELAY);
/* deassert reset */
if (mod->desc->powergate_ids[0] != -1) {
tegra_powergate_mc_flush_done(mod->desc->powergate_ids[0]);
tegra_periph_reset_deassert(mod->clk[0]);
tegra_powergate_mc_enable(mod->desc->powergate_ids[0]);
}
if (mod->desc->powergate_ids[1] != -1) {
tegra_powergate_mc_flush_done(mod->desc->powergate_ids[1]);
tegra_periph_reset_deassert(mod->clk[1]);
tegra_powergate_mc_enable(mod->desc->powergate_ids[1]);
}
dev_dbg(dev, "%s: module %s out of reset\n",
__func__, mod->name);
}
static int tegra_camera_enable_clk(struct tegra_camera_dev *dev)
{
if(tegra3_get_project_id() != TEGRA3_PROJECT_TF201)
tegra_pinmux_set_tristate(TEGRA_PINGROUP_CAM_MCLK, TEGRA_TRI_TRISTATE);
clk_enable(dev->vi_clk);
clk_enable(dev->vi_sensor_clk);
clk_enable(dev->csus_clk);
tegra_periph_reset_assert(dev->vi_clk);
udelay(2);
tegra_periph_reset_deassert(dev->vi_clk);
clk_enable(dev->isp_clk);
tegra_periph_reset_assert(dev->isp_clk);
udelay(2);
tegra_periph_reset_deassert(dev->isp_clk);
clk_enable(dev->csi_clk);
tegra_periph_reset_assert(dev->csi_clk);
udelay(2);
tegra_periph_reset_deassert(dev->csi_clk);
return 0;
}
void powergate_partition_deassert_reset(struct powergate_partition_info *pg_info)
{
u32 idx;
struct clk *clk_ptr;
struct partition_clk_info *clk_info;
for (idx = 0; idx < MAX_CLK_EN_NUM; idx++) {
clk_info = &pg_info->clk_info[idx];
clk_ptr = clk_info->clk_ptr;
if (!clk_ptr)
break;
if (clk_info->clk_type != CLK_ONLY)
tegra_periph_reset_deassert(clk_ptr);
}
}
static int tegra_camera_reset(struct tegra_camera_dev *dev, uint id)
{
struct clk *clk;
int mc_client = -1;
switch (id) {
case TEGRA_CAMERA_MODULE_VI:
clk = dev->vi_clk;
mc_client = TEGRA_POWERGATE_VENC;
break;
case TEGRA_CAMERA_MODULE_ISP:
clk = dev->isp_clk;
mc_client = TEGRA_POWERGATE_VENC;
break;
case TEGRA_CAMERA_MODULE_CSI:
clk = dev->csi_clk;
break;
default:
return -EINVAL;
}
if (mc_client != -1) {
tegra_powergate_mc_disable(mc_client);
}
tegra_periph_reset_assert(clk);
if (mc_client != -1) {
tegra_powergate_mc_flush(mc_client);
}
udelay(10);
if (mc_client != -1) {
tegra_powergate_mc_flush_done(mc_client);
}
tegra_periph_reset_deassert(clk);
if (mc_client != -1) {
tegra_powergate_mc_enable(mc_client);
}
return 0;
}
static void tegra_dsi_set_dsi_clk(struct tegra_dc *dc,
struct tegra_dc_dsi_data *dsi, u32 clk)
{
u32 rm;
rm = clk % 1000;
if (rm != 0)
clk -= rm;
clk *= 2; /* Value for PLLD routine is required to be twice as */
/* the desired clock rate */
dc->mode.pclk = clk*1000;
tegra_dc_setup_clk(dc, dsi->dsi_clk);
clk_enable(dsi->dsi_clk);
tegra_periph_reset_deassert(dsi->dsi_clk);
dsi->current_dsi_clk_khz = clk_get_rate(dsi->dsi_clk) / 1000;
dsi->current_bit_clk_ns = 1000*1000 / (dsi->current_dsi_clk_khz * 2);
}
static int tegra_camera_reset(uint id)
{
struct clk *clk;
switch (id) {
case TEGRA_CAMERA_MODULE_VI:
clk = vi_clk;
break;
case TEGRA_CAMERA_MODULE_ISP:
clk = isp_clk;
break;
case TEGRA_CAMERA_MODULE_CSI:
clk = csi_clk;
break;
default:
return -EINVAL;
}
tegra_periph_reset_assert(clk);
udelay(10);
tegra_periph_reset_deassert(clk);
return 0;
}
static int tegra30_ahub_probe(struct platform_device *pdev)
{
const struct of_device_id *match;
const struct tegra30_ahub_soc_data *soc_data;
struct clk *clk;
int i;
struct resource *res0, *res1, *region;
u32 of_dma[2];
void __iomem *regs_apbif, *regs_ahub;
int ret = 0;
if (ahub)
return -ENODEV;
match = of_match_device(tegra30_ahub_of_match, &pdev->dev);
if (!match)
return -EINVAL;
soc_data = match->data;
/*
* The AHUB hosts a register bus: the "configlink". For this to
* operate correctly, all devices on this bus must be out of reset.
* Ensure that here.
*/
for (i = 0; i < ARRAY_SIZE(configlink_clocks); i++) {
if (!(configlink_clocks[i].clk_list_mask &
soc_data->clk_list_mask))
continue;
clk = clk_get(&pdev->dev, configlink_clocks[i].clk_name);
if (IS_ERR(clk)) {
dev_err(&pdev->dev, "Can't get clock %s\n",
configlink_clocks[i].clk_name);
ret = PTR_ERR(clk);
goto err;
}
tegra_periph_reset_deassert(clk);
clk_put(clk);
}
ahub = devm_kzalloc(&pdev->dev, sizeof(struct tegra30_ahub),
GFP_KERNEL);
if (!ahub) {
dev_err(&pdev->dev, "Can't allocate tegra30_ahub\n");
ret = -ENOMEM;
goto err;
}
dev_set_drvdata(&pdev->dev, ahub);
ahub->dev = &pdev->dev;
ahub->clk_d_audio = clk_get(&pdev->dev, "d_audio");
if (IS_ERR(ahub->clk_d_audio)) {
dev_err(&pdev->dev, "Can't retrieve ahub d_audio clock\n");
ret = PTR_ERR(ahub->clk_d_audio);
goto err;
}
ahub->clk_apbif = clk_get(&pdev->dev, "apbif");
if (IS_ERR(ahub->clk_apbif)) {
dev_err(&pdev->dev, "Can't retrieve ahub apbif clock\n");
ret = PTR_ERR(ahub->clk_apbif);
goto err_clk_put_d_audio;
}
if (of_property_read_u32_array(pdev->dev.of_node,
"nvidia,dma-request-selector",
of_dma, 2) < 0) {
dev_err(&pdev->dev,
"Missing property nvidia,dma-request-selector\n");
ret = -ENODEV;
goto err_clk_put_d_audio;
}
ahub->dma_sel = of_dma[1];
res0 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res0) {
dev_err(&pdev->dev, "No apbif memory resource\n");
ret = -ENODEV;
goto err_clk_put_apbif;
}
region = devm_request_mem_region(&pdev->dev, res0->start,
resource_size(res0), DRV_NAME);
if (!region) {
dev_err(&pdev->dev, "request region apbif failed\n");
ret = -EBUSY;
goto err_clk_put_apbif;
}
ahub->apbif_addr = res0->start;
regs_apbif = devm_ioremap(&pdev->dev, res0->start,
resource_size(res0));
if (!regs_apbif) {
dev_err(&pdev->dev, "ioremap apbif failed\n");
ret = -ENOMEM;
goto err_clk_put_apbif;
}
ahub->regmap_apbif = devm_regmap_init_mmio(&pdev->dev, regs_apbif,
&tegra30_ahub_apbif_regmap_config);
if (IS_ERR(ahub->regmap_apbif)) {
dev_err(&pdev->dev, "apbif regmap init failed\n");
ret = PTR_ERR(ahub->regmap_apbif);
goto err_clk_put_apbif;
}
regcache_cache_only(ahub->regmap_apbif, true);
res1 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
if (!res1) {
dev_err(&pdev->dev, "No ahub memory resource\n");
ret = -ENODEV;
goto err_clk_put_apbif;
}
region = devm_request_mem_region(&pdev->dev, res1->start,
resource_size(res1), DRV_NAME);
if (!region) {
dev_err(&pdev->dev, "request region ahub failed\n");
ret = -EBUSY;
goto err_clk_put_apbif;
}
regs_ahub = devm_ioremap(&pdev->dev, res1->start,
resource_size(res1));
if (!regs_ahub) {
dev_err(&pdev->dev, "ioremap ahub failed\n");
ret = -ENOMEM;
goto err_clk_put_apbif;
}
ahub->regmap_ahub = devm_regmap_init_mmio(&pdev->dev, regs_ahub,
&tegra30_ahub_ahub_regmap_config);
if (IS_ERR(ahub->regmap_ahub)) {
dev_err(&pdev->dev, "ahub regmap init failed\n");
ret = PTR_ERR(ahub->regmap_ahub);
goto err_clk_put_apbif;
}
regcache_cache_only(ahub->regmap_ahub, true);
pm_runtime_enable(&pdev->dev);
if (!pm_runtime_enabled(&pdev->dev)) {
ret = tegra30_ahub_runtime_resume(&pdev->dev);
if (ret)
goto err_pm_disable;
}
of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
return 0;
err_pm_disable:
pm_runtime_disable(&pdev->dev);
err_clk_put_apbif:
clk_put(ahub->clk_apbif);
err_clk_put_d_audio:
clk_put(ahub->clk_d_audio);
ahub = NULL;
err:
return ret;
}
static int tegra_uart_hw_init(struct tegra_uart_port *tup)
{
int ret;
tup->fcr_shadow = 0;
tup->mcr_shadow = 0;
tup->lcr_shadow = 0;
tup->ier_shadow = 0;
tup->current_baud = 0;
clk_prepare_enable(tup->uart_clk);
/* Reset the UART controller to clear all previous status.*/
tegra_periph_reset_assert(tup->uart_clk);
udelay(10);
tegra_periph_reset_deassert(tup->uart_clk);
tup->rx_in_progress = 0;
tup->tx_in_progress = 0;
/*
* Set the trigger level
*
* For PIO mode:
*
* For receive, this will interrupt the CPU after that many number of
* bytes are received, for the remaining bytes the receive timeout
* interrupt is received. Rx high watermark is set to 4.
*
* For transmit, if the trasnmit interrupt is enabled, this will
* interrupt the CPU when the number of entries in the FIFO reaches the
* low watermark. Tx low watermark is set to 16 bytes.
*
* For DMA mode:
*
* Set the Tx trigger to 16. This should match the DMA burst size that
* programmed in the DMA registers.
*/
tup->fcr_shadow = UART_FCR_ENABLE_FIFO;
tup->fcr_shadow |= UART_FCR_R_TRIG_01;
tup->fcr_shadow |= TEGRA_UART_TX_TRIG_16B;
tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
/*
* Initialize the UART with default configuration
* (115200, N, 8, 1) so that the receive DMA buffer may be
* enqueued
*/
tup->lcr_shadow = TEGRA_UART_DEFAULT_LSR;
tegra_set_baudrate(tup, TEGRA_UART_DEFAULT_BAUD);
tup->fcr_shadow |= UART_FCR_DMA_SELECT;
tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
ret = tegra_uart_start_rx_dma(tup);
if (ret < 0) {
dev_err(tup->uport.dev, "Not able to start Rx DMA\n");
return ret;
}
tup->rx_in_progress = 1;
/*
* Enable IE_RXS for the receive status interrupts like line errros.
* Enable IE_RX_TIMEOUT to get the bytes which cannot be DMA'd.
*
* If using DMA mode, enable EORD instead of receive interrupt which
* will interrupt after the UART is done with the receive instead of
* the interrupt when the FIFO "threshold" is reached.
*
* EORD is different interrupt than RX_TIMEOUT - RX_TIMEOUT occurs when
* the DATA is sitting in the FIFO and couldn't be transferred to the
* DMA as the DMA size alignment(4 bytes) is not met. EORD will be
* triggered when there is a pause of the incomming data stream for 4
* characters long.
*
* For pauses in the data which is not aligned to 4 bytes, we get
* both the EORD as well as RX_TIMEOUT - SW sees RX_TIMEOUT first
* then the EORD.
*/
tup->ier_shadow = UART_IER_RLSI | UART_IER_RTOIE | TEGRA_UART_IER_EORD;
tegra_uart_write(tup, tup->ier_shadow, UART_IER);
return 0;
}
static int tegra_uart_hw_init(struct tegra_uart_port *t)
{
unsigned char ier;
unsigned char sir;
dev_vdbg(t->uport.dev, "+tegra_uart_hw_init\n");
t->fcr_shadow = 0;
t->mcr_shadow = 0;
t->lcr_shadow = 0;
t->ier_shadow = 0;
t->baud = 0;
pm_runtime_get_sync((&t->uport)->dev);
clk_prepare_enable(t->clk);
/* Reset the UART controller to clear all previous status.*/
tegra_periph_reset_assert(t->clk);
udelay(100);
tegra_periph_reset_deassert(t->clk);
udelay(100);
t->rx_in_progress = 0;
/*
* Set the trigger level
*
* For PIO mode:
*
* For receive, this will interrupt the CPU after that many number of
* bytes are received, for the remaining bytes the receive timeout
* interrupt is received.
*
* Rx high watermark is set to 4.
*
* For transmit, if the trasnmit interrupt is enabled, this will
* interrupt the CPU when the number of entries in the FIFO reaches the
* low watermark.
*
* Tx low watermark is set to 8.
*
* For DMA mode:
*
* Set the Tx trigger to 4. This should match the DMA burst size that
* programmed in the DMA registers.
*/
t->fcr_shadow = UART_FCR_ENABLE_FIFO;
t->fcr_shadow |= UART_FCR_R_TRIG_01;
t->fcr_shadow |= TEGRA_UART_TX_TRIG_8B;
uart_writeb(t, t->fcr_shadow, UART_FCR);
if (t->use_rx_dma) {
/*
* Initialize the UART for a simple default configuration
* so that the receive DMA buffer may be enqueued */
t->lcr_shadow = 3; /* no parity, stop, 8 data bits */
tegra_set_baudrate(t, 115200);
t->fcr_shadow |= UART_FCR_DMA_SELECT;
uart_writeb(t, t->fcr_shadow, UART_FCR);
if (tegra_start_dma_rx(t)) {
dev_err(t->uport.dev, "Rx DMA enqueue failed\n");
tegra_uart_free_rx_dma(t);
t->fcr_shadow &= ~UART_FCR_DMA_SELECT;
uart_writeb(t, t->fcr_shadow, UART_FCR);
}
} else {
uart_writeb(t, t->fcr_shadow, UART_FCR);
}
t->rx_in_progress = 1;
/*
* Enable IE_RXS for the receive status interrupts like line errros.
* Enable IE_RX_TIMEOUT to get the bytes which cannot be DMA'd.
*
* If using DMA mode, enable EORD instead of receive interrupt which
* will interrupt after the UART is done with the receive instead of
* the interrupt when the FIFO "threshold" is reached.
*
* EORD is different interrupt than RX_TIMEOUT - RX_TIMEOUT occurs when
* the DATA is sitting in the FIFO and couldn't be transferred to the
* DMA as the DMA size alignment(4 bytes) is not met. EORD will be
* triggered when there is a pause of the incomming data stream for 4
* characters long.
*
* For pauses in the data which is not aligned to 4 bytes, we get
* both the EORD as well as RX_TIMEOUT - SW sees RX_TIMEOUT first
* then the EORD.
*
* Don't get confused, believe in the magic of nvidia hw...:-)
*/
ier = 0;
ier |= UART_IER_RLSI | UART_IER_RTOIE;
if (t->use_rx_dma)
ier |= UART_IER_EORD;
else
ier |= UART_IER_RDI;
t->ier_shadow = ier;
uart_writeb(t, ier, UART_IER);
/*
* Tegra UART controller also support SIR PHY
* Enabled IRDA will transmit each zero bit as a short IR pulse.
*/
if (t->is_irda) {
dev_vdbg(t->uport.dev, "SIR enabled\n");
sir = TEGRA_UART_SIR_ENABLED;
uart_writeb(t, sir, TEGRA_UART_IRDA_CSR);
}
t->uart_state = TEGRA_UART_OPENED;
dev_vdbg(t->uport.dev, "-tegra_uart_hw_init\n");
return 0;
}
static int tegra_ehci_probe(struct platform_device *pdev)
{
struct resource *res;
struct usb_hcd *hcd;
struct tegra_ehci_hcd *tegra;
int err = 0;
int irq;
pr_info("%s: ehci.id = %d\n", __func__, pdev->id);
device_ehci_shutdown = false;
tegra = devm_kzalloc(&pdev->dev, sizeof(struct tegra_ehci_hcd),
GFP_KERNEL);
if (!tegra) {
dev_err(&pdev->dev, "memory alloc failed\n");
return -ENOMEM;
}
mutex_init(&tegra->sync_lock);
hcd = usb_create_hcd(&tegra_ehci_hc_driver, &pdev->dev,
dev_name(&pdev->dev));
if (!hcd) {
dev_err(&pdev->dev, "unable to create HCD\n");
return -ENOMEM;
}
platform_set_drvdata(pdev, tegra);
//+Sophia:0608
tegra->clk = clk_get(&pdev->dev, NULL);
if (IS_ERR(tegra->clk)) {
dev_err(&pdev->dev, "Can't get ehci clock\n");
err = PTR_ERR(tegra->clk);
goto fail_io;
}
err = clk_enable(tegra->clk);
if (err)
goto fail_clken;
tegra_periph_reset_assert(tegra->clk);
udelay(2);
tegra_periph_reset_deassert(tegra->clk);
udelay(2);
//+Sophia:0608
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(&pdev->dev, "failed to get I/O memory\n");
err = -ENXIO;
goto fail_io;
}
hcd->rsrc_start = res->start;
hcd->rsrc_len = resource_size(res);
hcd->regs = ioremap(res->start, resource_size(res));
if (!hcd->regs) {
dev_err(&pdev->dev, "failed to remap I/O memory\n");
err = -ENOMEM;
goto fail_io;
}
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
dev_err(&pdev->dev, "failed to get IRQ\n");
err = -ENODEV;
goto fail_irq;
}
set_irq_flags(irq, IRQF_VALID);
tegra->irq = irq;
tegra->phy = tegra_usb_phy_open(pdev);
if (IS_ERR(tegra->phy)) {
dev_err(&pdev->dev, "failed to open USB phy\n");
err = -ENXIO;
goto fail_irq;
}
err = tegra_usb_phy_power_on(tegra->phy);
if (err) {
dev_err(&pdev->dev, "failed to power on the phy\n");
goto fail_phy;
}
err = tegra_usb_phy_init(tegra->phy);
if (err) {
dev_err(&pdev->dev, "failed to init the phy\n");
goto fail_phy;
}
err = usb_add_hcd(hcd, irq, IRQF_SHARED | IRQF_TRIGGER_HIGH);
if (err) {
dev_err(&pdev->dev, "Failed to add USB HCD, error=%d\n", err);
goto fail_phy;
}
err = enable_irq_wake(tegra->irq);
if (err < 0) {
dev_warn(&pdev->dev,
"Couldn't enable USB host mode wakeup, irq=%d, "
"error=%d\n", irq, err);
err = 0;
tegra->irq = 0;
}
tegra->ehci = hcd_to_ehci(hcd);
//htc++
#ifdef CONFIG_QCT_9K_MODEM
if (Modem_is_QCT_MDM9K())
{
extern struct platform_device tegra_ehci2_device;
if (&tegra_ehci2_device == pdev)
{
mdm_hsic_ehci_hcd = tegra->ehci;
mdm_hsic_usb_hcd = hcd;
mdm_hsic_phy = tegra->phy;
pr_info("%s:: mdm_hsic_ehci_hcd = %x, mdm_hsic_usb_hcd = %x, mdm_hsic_phy = %x\n",
__func__, (unsigned int)mdm_hsic_ehci_hcd, (unsigned int)mdm_hsic_usb_hcd, (unsigned int)mdm_hsic_phy);
}
}
#endif //CONFIG_QCT_9K_MODEM
//htc--
#ifdef CONFIG_USB_OTG_UTILS
if (tegra_usb_phy_otg_supported(tegra->phy)) {
tegra->transceiver = otg_get_transceiver();
if (tegra->transceiver)
otg_set_host(tegra->transceiver, &hcd->self);
}
#endif
return err;
fail_phy:
tegra_usb_phy_close(tegra->phy);
fail_irq:
iounmap(hcd->regs);
fail_clken:
clk_put(tegra->clk);
fail_io:
usb_put_hcd(hcd);
return err;
}
