static int tegra20_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
cpu = cpu_logical_map(cpu);
/*
* Force the CPU into reset. The CPU must remain in reset when
* the flow controller state is cleared (which will cause the
* flow controller to stop driving reset if the CPU has been
* power-gated via the flow controller). This will have no
* effect on first boot of the CPU since it should already be
* in reset.
*/
tegra_put_cpu_in_reset(cpu);
/*
* Unhalt the CPU. If the flow controller was used to
* power-gate the CPU this will cause the flow controller to
* stop driving reset. The CPU will remain in reset because the
* clock and reset block is now driving reset.
*/
flowctrl_write_cpu_halt(cpu, 0);
tegra_enable_cpu_clock(cpu);
flowctrl_write_cpu_csr(cpu, 0); /* Clear flow controller CSR. */
tegra_cpu_out_of_reset(cpu);
return 0;
}
static int __cpuinit tegra_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
int status;
/*
* Force the CPU into reset. The CPU must remain in reset when the
* flow controller state is cleared (which will cause the flow
* controller to stop driving reset if the CPU has been power-gated
* via the flow controller). This will have no effect on first boot
* of the CPU since it should already be in reset.
*/
tegra_put_cpu_in_reset(cpu);
/*
* Unhalt the CPU. If the flow controller was used to power-gate the
* CPU this will cause the flow controller to stop driving reset.
* The CPU will remain in reset because the clock and reset block
* is now driving reset.
*/
flowctrl_write_cpu_halt(cpu, 0);
switch (tegra_chip_id) {
case TEGRA20:
status = tegra20_power_up_cpu(cpu);
break;
case TEGRA30:
status = tegra30_power_up_cpu(cpu);
break;
default:
status = -EINVAL;
break;
}
if (status)
goto done;
/* Take the CPU out of reset. */
tegra_cpu_out_of_reset(cpu);
done:
return status;
}
static int tegra30_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
int ret;
unsigned long timeout;
cpu = cpu_logical_map(cpu);
tegra_put_cpu_in_reset(cpu);
flowctrl_write_cpu_halt(cpu, 0);
/*
* The power up sequence of cold boot CPU and warm boot CPU
* was different.
*
* For warm boot CPU that was resumed from CPU hotplug, the
* power will be resumed automatically after un-halting the
* flow controller of the warm boot CPU. We need to wait for
* the confirmaiton that the CPU is powered then removing
* the IO clamps.
* For cold boot CPU, do not wait. After the cold boot CPU be
* booted, it will run to tegra_secondary_init() and set
* tegra_cpu_init_mask which influences what tegra30_boot_secondary()
* next time around.
*/
if (cpumask_test_cpu(cpu, &tegra_cpu_init_mask)) {
timeout = jiffies + msecs_to_jiffies(50);
do {
if (tegra_pmc_cpu_is_powered(cpu))
goto remove_clamps;
udelay(10);
} while (time_before(jiffies, timeout));
}
/*
* The power status of the cold boot CPU is power gated as
* default. To power up the cold boot CPU, the power should
* be un-gated by un-toggling the power gate register
* manually.
*/
if (!tegra_pmc_cpu_is_powered(cpu)) {
ret = tegra_pmc_cpu_power_on(cpu);
if (ret)
return ret;
/* Wait for the power to come up. */
timeout = jiffies + msecs_to_jiffies(100);
while (!tegra_pmc_cpu_is_powered(cpu)) {
if (time_after(jiffies, timeout))
return -ETIMEDOUT;
udelay(10);
}
}
remove_clamps:
/* CPU partition is powered. Enable the CPU clock. */
tegra_enable_cpu_clock(cpu);
udelay(10);
/* Remove I/O clamps. */
ret = tegra_pmc_cpu_remove_clamping(cpu);
if (ret)
return ret;
udelay(10);
flowctrl_write_cpu_csr(cpu, 0); /* Clear flow controller CSR. */
tegra_cpu_out_of_reset(cpu);
return 0;
}
