static int _send_int(SerialPort *port, unsigned char* buf, int bsize)
{
int i;
unsigned long pretime;
for (i = 0; i < bsize; i++)
{
if (port->TxTimeOut < 0) {
while (QueueFull(port->xmit));
} else {
pretime = timer_NowTime();
while (QueueFull(port->xmit) && (timer_NowTime() - pretime) < port->TxTimeOut);
if (QueueFull(port->xmit)) {
if (UART_TIMEOUT_DEBUG)
err_print((char*)"%s: COM%d transmit timeout.\n", __FUNCTION__, port->com + 1);
if (!(port->ier & THREI)) io_outpb(port->IER, port->ier |= THREI);
return i;
}
}
io_DisableINT();
{
PushQueue(port->xmit, buf[i]);
if (!(port->ier & THREI) && (i == (bsize - 1) || QueueFull(port->xmit)))
{
switch (port->control)
{
case NO_CONTROL:
{
io_outpb(port->IER, port->ier |= THREI);
}
break;
case RTS_CTS:
{
if (port->cts == CTS_ON) {
io_outpb(port->IER, port->ier |= THREI);
}
}
break;
case XON_XOFF:
{
if (port->xonxoff_rcvd != XOFF_RCVD) {
io_outpb(port->IER, port->ier |= THREI);
}
}
break;
default: break;
};
}
}
io_RestoreINT();
}
return i;
}
DMPAPI(bool) i2cslave_Write(int dev, unsigned char val) {
unsigned long nowtime;
if (I2C_action[dev] != I2CACT_SLAVEWRITEREQ)
{
err_print("slave must write data only when being requested");
return false;
}
i2cslave_ClearSlaveWREQ(dev);
i2c_WriteDataREG(dev, val);
for (nowtime=0; nowtime<100000L; nowtime++) //trick for performance; timer_NowTime() is time-consuming in some OS
if (i2c_CheckTXDone(dev) == true) goto TX_SUCCESS;
nowtime = timer_NowTime();
while ((i2c_CheckTXDone(dev) == false) && ((timer_NowTime() - nowtime) < I2C_TIMEOUT));
if (i2c_CheckTXDone(dev) == false)
{
err_print("the I2C module doesn't respond");
I2C_action[dev] = I2CACT_IDLE;
return false;
}
TX_SUCCESS:
i2c_ClearTXDone(dev);
I2C_action[dev] = I2CACT_SLAVE;
return true;
}
DMP_INLINE(bool) check_RX_done(int dev) {
unsigned long nowtime;
unsigned char statreg;
for (nowtime=0; nowtime<100000L; nowtime++) //trick for speed; timer_NowTime() is time-consuming in some OS
if (i2c_CheckRXRdy(dev) == true) goto RX_SUCCESS;
nowtime = timer_NowTime();
while ((i2c_CheckRXRdy(dev) == false) && ((timer_NowTime() - nowtime) < I2C_TIMEOUT));
RX_SUCCESS:
statreg = i2c_ReadStatREG(dev); //ugly code for speed:p
i2c_ClearRXRdy(dev);
if ((statreg & 0x08) != 0) //if (i2cmaster_CheckARLoss(dev) == true)
{
err_print("arbitration loss for I2C bus");
i2cmaster_ClearARLoss(dev);
return false;
}
if ((statreg & 0x01) == 0) //if (i2c_IsMaster(dev) == false)
{
err_print("I2C%d module isn't in Master Mode", dev);
return false;
}
if ((statreg & 0x40) == 0) //if (i2c_CheckRXRdy(dev) == false)
{
err_print("I2C%d module doesn't respond", dev);
return false;
}
return true;
}
static int _recv_int(SerialPort *port, unsigned char* buf, int bsize)
{
int i;
unsigned long pretime;
for (i = 0; i < bsize; i++)
{
if (port->RxTimeOut < 0) {
while (QueueEmpty(port->rcvd));
} else {
pretime = timer_NowTime();
while (QueueEmpty(port->rcvd) && (timer_NowTime() - pretime) < port->RxTimeOut);
if (QueueEmpty(port->rcvd)) {
if (UART_TIMEOUT_DEBUG)
err_print((char*)"%s: COM%d receive timeout.\n", __FUNCTION__, port->com + 1);
break;
}
}
io_DisableINT();
{
buf[i] = PopQueue(port->rcvd);
switch (port->control)
{
case NO_CONTROL: break;
case RTS_CTS:
{
if (QueueSize(port->rcvd) < (RX_QUEUE_SIZE - NEAR_FULL_SIZE) && port->rts == 0) {
io_outpb(port->MCR, io_inpb(port->MCR) | 0x02);
port->rts = 1;
}
}
break;
case XON_XOFF:
{
if (QueueSize(port->rcvd) < (RX_QUEUE_SIZE - NEAR_FULL_SIZE) && port->xonxoff_xmit != XON_XMIT) {
port->xon = 1;
io_outpb(port->IER, port->ier |= 0x02);
}
}
break;
default: break;
};
}
io_RestoreINT();
}
return i;
}
DMP_INLINE(bool) check_STOP_done(int dev) {
unsigned long nowtime;
for (nowtime=0; nowtime<100000L; nowtime++) //trick for speed; timer_NowTime() is time-consuming in some OS
if (i2cmaster_CheckStopBit(dev) == false) goto STOP_SUCCESS;
nowtime = timer_NowTime();
while ((i2cmaster_CheckStopBit(dev) == true) && ((timer_NowTime() - nowtime) < I2C_TIMEOUT));
if (i2cmaster_CheckStopBit(dev) == true)
{
err_print("fail to stop the transaction");
return false;
}
STOP_SUCCESS:
return true;
}
DMPAPI(bool) i2c_Reset(int dev) {
unsigned long nowtime;
io_outpb(I2C_EXCTRL_REG(dev), io_inpb(I2C_EXCTRL_REG(dev)) | 0x80);
nowtime = timer_NowTime();
while (((io_inpb(I2C_EXCTRL_REG(dev)) & 0x80) != 0) && ((timer_NowTime() - nowtime) < I2C_TIMEOUT));
if ((io_inpb(I2C_EXCTRL_REG(dev)) & 0x80) != 0)
{
err_print("fail to reset I2C module %d", dev);
return false;
}
//Remarks: due to Vortex86DX's poor I2C design, RESET bit may become 0 when dummy clocks are still being output
timer_Delay(20L); //lazy trick to tackle the above issue
return true;
}
bool init() {
int i, crossbarBase, gpioBase;
if(io_Init() == false) return false;
timer_NowTime(); // initialize timer
CLOCKS_PER_MICROSEC = vx86_CpuCLK();
VORTEX86EX_CLOCKS_PER_MS = CLOCKS_PER_MICROSEC*1000UL;
// Set IRQ4 as level-trigger
io_outpb(0x4D0, io_inpb(0x4D0) | 0x10);
//set corssbar Base Address
crossbarBase = sb_Read16(SB_CROSSBASE) & 0xfffe;
if(crossbarBase == 0 || crossbarBase == 0xfffe)
sb_Write16(SB_CROSSBASE, CROSSBARBASE | 0x01);
// Force set HIGH speed ISA on SB
sb_Write(SB_FCREG, sb_Read(SB_FCREG) | 0x8000C000L);
//set SB GPIO Base Address
gpioBase = sb_Read16(SB_GPIOBASE) & 0xfffe;
if(gpioBase == 0 || gpioBase == 0xfffe)
{
sb_Write16(SB_GPIOBASE, GPIOCTRLBASE | 0x01);
gpioBase = GPIOCTRLBASE;
}
// Enable GPIO 0 ~ 7
io_outpdw(gpioBase, 0x00ff);
// set GPIO Port 0~7 dircetion & data Address
for(i=0;i<8;i++)
io_outpdw(gpioBase + (i+1)*4,((GPIODIRBASE + i*4)<<16) + GPIODATABASE + i*4);
// set ADC Base Address
sb_Write(0xbc, sb_Read(0xbc) & (~(1L<<28))); // active adc
sb1_Write16(0xde, sb1_Read16(0xde) | 0x02); // not Available for 8051A Access ADC
sb1_Write(0xe0, 0x0050fe00L); // baseaddr = 0xfe00, disable irq
// set MCM Base Address
set_MMIO();
mc_setbaseaddr();
for(i=0; i<4; i++)
mc_SetMode(i, MCMODE_PWM_SIFB);
if(Global_irq_Init == false)
{
// set MCM IRQ
if(irq_Init() == false)
{
printf("MCM IRQ init fail\n"); return false;
}
if(irq_Setting(GetMCIRQ(), IRQ_LEVEL_TRIGGER + IRQ_DISABLE_INTR) == false)
{
printf("MCM IRQ Setting fail\n"); return false;
}
Set_MCIRQ(GetMCIRQ());
Global_irq_Init = true;
}
//CDC
USBDEV = CreateUSBDevice();
if(USBDEV == NULL)
{
printf("init error\n");
return false;
}
usb_SetUSBPins(USBDEV, 7, 0, 7, 1);
usb_SetTimeOut(USBDEV, 0L, 500L); // USB RX timerout is 0ms and TX timeout is 500ms
if(usb_Init(USBDEV) == false)
{
printf("init2 error\n");
return false;
}
//io_Close();
return true;
}
unsigned long millis() {
return timer_NowTime();
}
unsigned long long int Encoder::_pulseIn(uint8_t pin, uint8_t state, unsigned long timeout) {
unsigned long data, _timeout;
unsigned long long int povdata = 0L, result = 0L;
int stat;
if(_pcapAttchINT == true || mode != MODE_CAPTURE || pin > 2) return 0L;
_timeout = timer_NowTime() + timeout;
#if defined (DMP_DOS_BC) || (DMP_DOS_DJGPP)
if(state == HIGH)
{
while(1)
{
if(timeout != 0L && timer_NowTime() > _timeout) return 0L;
if(readCapStat[pin](mcn, MCSIF_MODULEB) != MCENC_CAPFIFO_EMPTY &&
readCapFIFO[pin](mcn, MCSIF_MODULEB, &data) == MCPFAU_CAP_0TO1EDGE)
break;
}
while(1)
{
if(timeout != 0L && timer_NowTime() > _timeout) return 0L;
if(readCapStat[pin](mcn, MCSIF_MODULEB) != MCENC_CAPFIFO_EMPTY)
{
stat = readCapFIFO[pin](mcn, MCSIF_MODULEB, &data);
if(stat == MCPFAU_CAP_CAPCNT_OVERFLOW)
povdata += 0x10000000L;
else if(stat == MCPFAU_CAP_1TO0EDGE)
{
result = data + povdata;
break;
}
}
}
}
else
{
while(1)
{
if(timeout != 0L && timer_NowTime() > _timeout) return 0L;
if(readCapStat[pin](mcn, MCSIF_MODULEB) != MCENC_CAPFIFO_EMPTY &&
readCapFIFO[pin](mcn, MCSIF_MODULEB, &data) == MCPFAU_CAP_1TO0EDGE)
break;
}
while(1)
{
if(timeout != 0L && timer_NowTime() > _timeout) return 0L;
if(readCapStat[pin](mcn, MCSIF_MODULEB) != MCENC_CAPFIFO_EMPTY)
{
stat = readCapFIFO[pin](mcn, MCSIF_MODULEB, &data);
if(stat == MCPFAU_CAP_CAPCNT_OVERFLOW)
povdata += 0x10000000L;
else if(stat == MCPFAU_CAP_0TO1EDGE)
{
result = data + povdata;
break;
}
}
}
}
#elif defined (DMP_LINUX)
lockMCMSIF();
if(state == HIGH)
{
while(1)
{
if(timeout != 0L && timer_NowTime() > _timeout) {unLockMCMSIF(); return 0L;}
if(readCapStat[pin](mcn, MCSIF_MODULEB) != MCENC_CAPFIFO_EMPTY &&
readCapFIFO[pin](mcn, MCSIF_MODULEB, &data) == MCPFAU_CAP_0TO1EDGE)
break;
}
while(1)
{
if(timeout != 0L && timer_NowTime() > _timeout) {unLockMCMSIF(); return 0L;}
if(readCapStat[pin](mcn, MCSIF_MODULEB) != MCENC_CAPFIFO_EMPTY)
{
stat = readCapFIFO[pin](mcn, MCSIF_MODULEB, &data);
if(stat == MCPFAU_CAP_CAPCNT_OVERFLOW)
povdata += 0x10000000L;
else if(stat == MCPFAU_CAP_1TO0EDGE)
{
result = data + povdata;
break;
}
}
}
}
else
{
while(1)
{
if(timeout != 0L && timer_NowTime() > _timeout) {unLockMCMSIF(); return 0L;}
if(readCapStat[pin](mcn, MCSIF_MODULEB) != MCENC_CAPFIFO_EMPTY &&
readCapFIFO[pin](mcn, MCSIF_MODULEB, &data) == MCPFAU_CAP_1TO0EDGE)
break;
}
while(1)
{
if(timeout != 0L && timer_NowTime() > _timeout) {unLockMCMSIF(); return 0L;}
if(readCapStat[pin](mcn, MCSIF_MODULEB) != MCENC_CAPFIFO_EMPTY)
{
stat = readCapFIFO[pin](mcn, MCSIF_MODULEB, &data);
if(stat == MCPFAU_CAP_CAPCNT_OVERFLOW)
povdata += 0x10000000L;
else if(stat == MCPFAU_CAP_0TO1EDGE)
{
result = data + povdata;
break;
}
}
}
}
#endif
return result;
}
