void torture_setup ( void ) {
rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM3EN);
timer_reset(TIM3);
// 24Mhz / 10khz -1.
timer_set_prescaler(TIM3, 20000); // 24Mhz/10000hz - 1
// 10khz for 10 ticks = 1 khz overflow = 1ms overflow interrupts
timer_set_period(TIM3, 1);
/* Set timer start value. */
TIM_CNT(TIM3) = 1;
/* Set timer prescaler. */
TIM_PSC(TIM3) = 100; // 100 .. so about 840000 ticks per second
/* End timer value. If this is reached an interrupt is generated. */
TIM_ARR(TIM3) = 60; // 840000/14 -> 60,000/sec
nvic_enable_irq(NVIC_TIM3_IRQ);
timer_enable_update_event(TIM3); // default at reset!
timer_enable_irq(TIM3, TIM_DIER_UIE);
timer_enable_counter(TIM3);
}
/**
* Setup stepper motors' timer Tim
* N == 0 for TIM3, == 1 for TIM4
*/
static void setup_timer(uint8_t N){
uint32_t Tim;
switch (N){
case 0:
Tim = TIM3;
nvic_enable_irq(NVIC_TIM3_IRQ);
break;
case 1:
Tim = TIM4;
nvic_enable_irq(NVIC_TIM4_IRQ);
break;
default:
return;
}
timer_reset(Tim);
// timers have frequency of 2MHz, 2 pulse == 1 microstep
// 36MHz of APB1
timer_set_mode(Tim, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
// 72MHz div 36 = 2MHz
timer_set_prescaler(Tim, 35); // prescaler is (div - 1), 2pulse == 1 step
timer_continuous_mode(Tim); // automatically reload
timer_disable_preload(Tim); // force changing period
timer_set_period(Tim, Motor_period[N] - 1);
timer_enable_update_event(Tim);
timer_enable_irq(Tim, TIM_DIER_UIE); // update IRQ enable
timer_enable_counter(Tim);
timers_activated[N] = 1;
#ifdef EBUG
if(mode == BYTE_MODE){
lastsendfun('3' + N);
P(" timer\n", lastsendfun);
}
#endif
}
/*
* Another ms timer, this one used to generate an overflow interrupt at 1ms
* It is used to toggle leds and write tick counts
*/
static void setup_tim6(void)
{
timer_reset(TIM6);
/* 24Mhz / 10khz -1. */
timer_set_prescaler(TIM6, 2399); /* 24Mhz/10000hz - 1 */
/* 10khz for 10 ticks = 1 khz overflow = 1ms overflow interrupts */
timer_set_period(TIM6, 10);
nvic_enable_irq(NVIC_TIM6_IRQ);
timer_enable_update_event(TIM6); /* default at reset! */
timer_enable_irq(TIM6, TIM_DIER_UIE);
timer_enable_counter(TIM6);
}
void PID_tim_init(void)
{
/* Enable TIM1 clock. and Port E clock (for outputs) */
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_TIM1EN);
rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPEEN);
//Set TIM1 channel (and complementary) output to alternate function push-pull'.
//f4 TIM1=> GIO9: CH1, GPIO11: CH2, GPIO13: CH3
//f4 TIM1=> GIO8: CH1N, GPIO10: CH2N, GPIO12: CH3N
gpio_mode_setup(GPIOE, GPIO_MODE_AF,GPIO_PUPD_NONE,GPIO9 | GPIO11 | GPIO13);
gpio_set_af(GPIOE, GPIO_AF1, GPIO9 | GPIO11 | GPIO13);
gpio_mode_setup(GPIOE, GPIO_MODE_AF,GPIO_PUPD_NONE,GPIO8 | GPIO10 | GPIO12);
gpio_set_af(GPIOE, GPIO_AF1, GPIO8 | GPIO10 | GPIO12);
/* Enable TIM1 commutation interrupt. */
//nvic_enable_irq(NVIC_TIM1_TRG_COM_TIM11_IRQ); //f4
/* Reset TIM1 peripheral. */
timer_reset(TIM1);
/* Timer global mode:
* - No divider
* - Alignment edge
* - Direction up
*/
timer_set_mode(TIM1, TIM_CR1_CKD_CK_INT, //For dead time and filter sampling, not important for now.
TIM_CR1_CMS_CENTER_3, //TIM_CR1_CMS_EDGE
//TIM_CR1_CMS_CENTER_1
//TIM_CR1_CMS_CENTER_2
//TIM_CR1_CMS_CENTER_3 la frequencia del pwm se divide a la mitad. (frecuencia senoidal)
TIM_CR1_DIR_UP);
timer_set_prescaler(TIM1, PRESCALE); //1 = disabled (max speed)
timer_set_repetition_counter(TIM1, 0); //disabled
timer_enable_preload(TIM1);
timer_continuous_mode(TIM1);
/* Period (32kHz). */
timer_set_period(TIM1, PWM_PERIOD_ARR); //ARR (value compared against main counter to reload counter aka: period of counter)
/* Configure break and deadtime. */
//timer_set_deadtime(TIM1, deadtime_percentage*pwm_period_ARR);
timer_set_enabled_off_state_in_idle_mode(TIM1);
timer_set_enabled_off_state_in_run_mode(TIM1);
timer_disable_break(TIM1);
timer_set_break_polarity_high(TIM1);
timer_disable_break_automatic_output(TIM1);
timer_set_break_lock(TIM1, TIM_BDTR_LOCK_OFF);
/* Disable outputs. */
timer_disable_oc_output(TIM1, TIM_OC1);
timer_disable_oc_output(TIM1, TIM_OC1N);
timer_disable_oc_output(TIM1, TIM_OC2);
timer_disable_oc_output(TIM1, TIM_OC2N);
timer_disable_oc_output(TIM1, TIM_OC3);
timer_disable_oc_output(TIM1, TIM_OC3N);
/* -- OC1 and OC1N configuration -- */
/* Configure global mode of line 1. */
timer_enable_oc_preload(TIM1, TIM_OC1);
timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_PWM1);
/* Configure OC1. */
timer_set_oc_polarity_high(TIM1, TIM_OC1);
timer_set_oc_idle_state_unset(TIM1, TIM_OC1); //When idle (braked) put 0 on output
/* Configure OC1N. */
timer_set_oc_polarity_high(TIM1, TIM_OC1N);
timer_set_oc_idle_state_unset(TIM1, TIM_OC1N);
/* Set the capture compare value for OC1. */
timer_set_oc_value(TIM1, TIM_OC1, INIT_DUTY*PWM_PERIOD_ARR);//initial_duty_cycle*pwm_period_ARR);
/* -- OC2 and OC2N configuration -- */
/* Configure global mode of line 2. */
timer_enable_oc_preload(TIM1, TIM_OC2);
timer_set_oc_mode(TIM1, TIM_OC2, TIM_OCM_PWM1);
/* Configure OC2. */
timer_set_oc_polarity_high(TIM1, TIM_OC2);
timer_set_oc_idle_state_unset(TIM1, TIM_OC2);
/* Configure OC2N. */
timer_set_oc_polarity_high(TIM1, TIM_OC2N);
timer_set_oc_idle_state_unset(TIM1, TIM_OC2N);
/* Set the capture compare value for OC2. */
timer_set_oc_value(TIM1, TIM_OC2, INIT_DUTY*PWM_PERIOD_ARR);//initial_duty_cycle*pwm_period_ARR);
/* -- OC3 and OC3N configuration -- */
/* Configure global mode of line 3. */
timer_enable_oc_preload(TIM1, TIM_OC3);
timer_set_oc_mode(TIM1, TIM_OC3, TIM_OCM_PWM1);
/* Configure OC3. */
timer_set_oc_polarity_high(TIM1, TIM_OC3);
timer_set_oc_idle_state_unset(TIM1, TIM_OC3);
/* Configure OC3N. */
timer_set_oc_polarity_high(TIM1, TIM_OC3N);
timer_set_oc_idle_state_unset(TIM1, TIM_OC3N);
/* Set the capture compare value for OC3. */
timer_set_oc_value(TIM1, TIM_OC3, INIT_DUTY*PWM_PERIOD_ARR);//initial_duty_cycle*pwm_period_ARR);//100);
/* Reenable outputs. */
timer_enable_oc_output(TIM1, TIM_OC1);
timer_enable_oc_output(TIM1, TIM_OC1N);
timer_enable_oc_output(TIM1, TIM_OC2);
timer_enable_oc_output(TIM1, TIM_OC2N);
timer_enable_oc_output(TIM1, TIM_OC3);
timer_enable_oc_output(TIM1, TIM_OC3N);
/* ---- */
/* ARR reload enable. */
timer_enable_preload(TIM1);
/*
* Enable preload of complementary channel configurations and
* update on COM event.
*/
//timer_enable_preload_complementry_enable_bits(TIM1);
timer_disable_preload_complementry_enable_bits(TIM1);
/* Enable outputs in the break subsystem. */
timer_enable_break_main_output(TIM1);
/* Generate update event to reload all registers before starting*/
timer_generate_event(TIM1, TIM_EGR_UG);
/* Counter enable. */
timer_enable_counter(TIM1);
/* Enable commutation interrupt. */
//timer_enable_irq(TIM1, TIM_DIER_COMIE);
/*********/
/*Capture compare interrupt*/
//enable capture compare interrupt
timer_enable_update_event(TIM1);
/* Enable commutation interrupt. */
//timer_enable_irq(TIM1, TIM_DIER_CC1IE); //Capture/compare 1 interrupt enable
/* Enable commutation interrupt. */
//timer_enable_irq(TIM1, TIM_DIER_CC1IE);
timer_enable_irq(TIM1, TIM_DIER_UIE);
nvic_enable_irq(NVIC_TIM1_UP_TIM10_IRQ);
}
