void __init tegra2_init_timer(u32 *offset, int *irq)
{
unsigned long rate = clk_measure_input_freq();
int ret;
switch (rate) {
case 12000000:
timer_writel(0x000b, TIMERUS_USEC_CFG);
break;
case 13000000:
timer_writel(0x000c, TIMERUS_USEC_CFG);
break;
case 19200000:
timer_writel(0x045f, TIMERUS_USEC_CFG);
break;
case 26000000:
timer_writel(0x0019, TIMERUS_USEC_CFG);
break;
default:
WARN(1, "Unknown clock rate");
}
#ifdef CONFIG_PM_SLEEP
ret = setup_irq(tegra_lp2wake_irq.irq, &tegra_lp2wake_irq);
if (ret) {
pr_err("Failed to register LP2 timer IRQ: %d\n", ret);
BUG();
}
#endif
*offset = TIMER3_OFFSET;
*irq = INT_TMR3;
}
void timer_stop(int timer_n)
{
u32 timern_base;
timern_base = get_timer_base(timer_n);
timer_writel(1 << 30, timern_base + TIMER_PCR);
timer_writel(0, timern_base + TIMER_PTV);
}
void tegra_lp2_set_trigger(unsigned long cycles)
{
timer_writel(0, TIMER4_BASE + TIMER_PTV);
if (cycles) {
u32 reg = 0x80000000ul | min(0x1ffffffful, cycles);
timer_writel(reg, TIMER4_BASE + TIMER_PTV);
}
}
void tegra3_lp2_set_trigger(unsigned long cycles)
{
int cpu = cpu_number();
int base;
base = lp2_wake_timers[cpu];
timer_writel(0, base + TIMER_PTV);
if (cycles) {
u32 reg = 0x80000000ul | min(0x1ffffffful, cycles);
timer_writel(reg, base + TIMER_PTV);
}
}
void tegra3_lp2_timer_cancel_secondary(void)
{
int cpu;
int base;
for (cpu = 1; cpu < ARRAY_SIZE(lp2_wake_timers); cpu++) {
base = lp2_wake_timers[cpu];
cpumask_set_cpu(cpu, &wake_timer_canceled);
timer_writel(0, base + TIMER_PTV);
timer_writel(1<<30, base + TIMER_PCR);
}
}
void tegra3_lp2_set_trigger(unsigned long cycles)
{
unsigned int cpu = smp_processor_id();
int base;
base = cpu_local_timers[cpu];
if (cycles) {
timer_writel(0, base + TIMER_PTV);
if (cycles) {
u32 reg = 0x80000000 | ((cycles > 1) ? (cycles-1) : 0);
timer_writel(reg, base + TIMER_PTV);
}
}
}
static void __init tegra_init_timer(void)
{
unsigned long rate = clk_measure_input_freq();
int ret;
#ifdef CONFIG_HAVE_ARM_TWD
twd_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x600);
#endif
switch (rate) {
case 12000000:
timer_writel(0x000b, TIMERUS_USEC_CFG);
break;
case 13000000:
timer_writel(0x000c, TIMERUS_USEC_CFG);
break;
case 19200000:
timer_writel(0x045f, TIMERUS_USEC_CFG);
break;
case 26000000:
timer_writel(0x0019, TIMERUS_USEC_CFG);
break;
default:
WARN(1, "Unknown clock rate");
}
if (clocksource_register_hz(&tegra_clocksource, 1000000)) {
printk(KERN_ERR "Failed to register clocksource\n");
BUG();
}
ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq);
if (ret) {
printk(KERN_ERR "Failed to register timer IRQ: %d\n", ret);
BUG();
}
clockevents_calc_mult_shift(&tegra_clockevent, 1000000, 5);
tegra_clockevent.max_delta_ns =
clockevent_delta2ns(0x1fffffff, &tegra_clockevent);
tegra_clockevent.min_delta_ns =
clockevent_delta2ns(0x1, &tegra_clockevent);
tegra_clockevent.cpumask = cpu_all_mask;
tegra_clockevent.irq = tegra_timer_irq.irq;
clockevents_register_device(&tegra_clockevent);
return;
}
static void tegra_timer_resume(void)
{
timer_writel(usec_config, TIMERUS_USEC_CFG);
usec_offset -= timer_readl(TIMERUS_CNTR_1US);
usec_suspended = false;
}
static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id)
{
struct clock_event_device *evt = (struct clock_event_device *)dev_id;
timer_writel(1<<30, system_timer + TIMER_PCR);
evt->event_handler(evt);
return IRQ_HANDLED;
}
static void test_lp2_wake_timer(unsigned int cpu)
{
unsigned long cycles = 50000;
unsigned int base = lp2_wake_timers[cpu];
static bool tested[4] = {false, false, false, false};
/* Don't repeat the test process on hotplug restart. */
if (!tested[cpu]) {
timer_writel(0, base + TIMER_PTV);
if (cycles) {
u32 reg = 0x80000000ul | min(0x1ffffffful, cycles);
timer_writel(reg, base + TIMER_PTV);
tested[cpu] = true;
}
}
}
void timer_interrupt_clear(int timer_n)
{
u32 timern_base;
timern_base = get_timer_base(timer_n);
/* clear interrupt */
timer_writel(1 << 30, timern_base + TIMER_PCR);
}
static int tegra_timer_set_periodic(struct clock_event_device *evt)
{
u32 reg = 0xC0000000 | ((1000000 / HZ) - 1);
timer_shutdown(evt);
timer_writel(reg, TIMER3_BASE + TIMER_PTV);
return 0;
}
static irqreturn_t tegra_lp2wake_interrupt(int irq, void *dev_id)
{
int cpu = (int)dev_id;
int base;
base = lp2_wake_timers[cpu];
timer_writel(1<<30, base + TIMER_PCR);
return IRQ_HANDLED;
}
static int tegra_timer_set_next_event(unsigned long cycles,
struct clock_event_device *evt)
{
u32 reg;
reg = 0x80000000 | ((cycles > 1) ? (cycles-1) : 0);
timer_writel(reg, system_timer + TIMER_PTV);
return 0;
}
static void tegra_timer_set_mode(enum clock_event_mode mode,
struct clock_event_device *evt)
{
u32 reg;
timer_writel(0, system_timer + TIMER_PTV);
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
reg = 0xC0000000 | ((1000000/HZ)-1);
timer_writel(reg, system_timer + TIMER_PTV);
break;
case CLOCK_EVT_MODE_ONESHOT:
break;
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
case CLOCK_EVT_MODE_RESUME:
break;
}
}
void timer_start(int timer_n, u32 count)
{
u32 timern_base;
if (count > 0x1fffffff)
{
printk(KERN_ERR "Invalid count length: %u\n", count);
return;
}
timern_base = get_timer_base(timer_n);
timer_writel((0x80000000 | count), timern_base + TIMER_PTV);
}
static irqreturn_t tegra_cputimer_interrupt(int irq, void *dev_id)
{
struct tegra_clock_event_device *clkevt = dev_id;
struct clock_event_device *evt = clkevt->evt;
int base;
unsigned int cpu;
cpu = cpumask_first(evt->cpumask);
base = cpu_local_timers[cpu];
timer_writel(1<<30, base + TIMER_PCR);
evt->event_handler(evt);
return IRQ_HANDLED;
}
static int tegra_cputimer_set_next_event(unsigned long cycles,
struct clock_event_device *evt)
{
u32 reg;
int base;
unsigned int cpu;
cpu = cpumask_first(evt->cpumask);
base = cpu_local_timers[cpu];
reg = 0x80000000 | ((cycles > 1) ? (cycles-1) : 0);
timer_writel(reg, base + TIMER_PTV);
return 0;
}
static void tegra_cputimer_set_mode(enum clock_event_mode mode,
struct clock_event_device *evt)
{
u32 reg;
int base;
unsigned int cpu;
cpu = cpumask_first(evt->cpumask);
base = cpu_local_timers[cpu];
timer_writel(0, base + TIMER_PTV);
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
reg = 0xC0000000 | ((1000000/HZ)-1);
timer_writel(reg, base + TIMER_PTV);
break;
case CLOCK_EVT_MODE_ONESHOT:
break;
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
case CLOCK_EVT_MODE_RESUME:
break;
}
}
static void __init tegra_init_timer(void)
{
unsigned long rate;
unsigned int m, n;
int ret;
#ifdef CONFIG_HAVE_ARM_TWD
twd_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x600);
#endif
rate = measure_input_freq(&m, &n);
timer_writel(((m-1)<<8 | (n-1)), TIMERUS_USEC_CFG);
tegra_clocksource_resume(NULL);
if (clocksource_register(&tegra_clocksource)) {
printk(KERN_ERR "Failed to register clocksource\n");
BUG();
}
ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq);
if (ret) {
printk(KERN_ERR "Failed to register timer IRQ: %d\n", ret);
BUG();
}
ret = setup_irq(tegra_lp2wake_irq.irq, &tegra_lp2wake_irq);
if (ret) {
printk(KERN_ERR "Failed to register LP2 timer IRQ: %d\n", ret);
BUG();
}
tegra_clockevent.max_delta_ns =
clockevent_delta2ns(0x1fffffff, &tegra_clockevent);
tegra_clockevent.min_delta_ns =
clockevent_delta2ns(0x1, &tegra_clockevent);
tegra_clockevent.cpumask = cpu_all_mask;
tegra_clockevent.irq = tegra_timer_irq.irq;
clockevents_register_device(&tegra_clockevent);
return;
}
void __init tegra3_init_timer(u32 *offset, int *irq)
{
unsigned long rate = tegra_clk_measure_input_freq();
switch (rate) {
case 12000000:
timer_writel(0x000b, TIMERUS_USEC_CFG);
break;
case 13000000:
timer_writel(0x000c, TIMERUS_USEC_CFG);
break;
case 19200000:
timer_writel(0x045f, TIMERUS_USEC_CFG);
break;
case 26000000:
timer_writel(0x0019, TIMERUS_USEC_CFG);
break;
case 16800000:
timer_writel(0x0453, TIMERUS_USEC_CFG);
break;
case 38400000:
timer_writel(0x04BF, TIMERUS_USEC_CFG);
break;
case 48000000:
timer_writel(0x002F, TIMERUS_USEC_CFG);
break;
default:
WARN(1, "Unknown clock rate");
}
#ifdef CONFIG_PM_SLEEP
#ifdef CONFIG_SMP
/* For T30.A01 use INT_TMR_SHARED instead of INT_TMR6 for CPU3. */
if ((tegra_get_chipid() == TEGRA_CHIPID_TEGRA3) &&
(tegra_get_revision() == TEGRA_REVISION_A01))
tegra_lp2wake_irq[3].irq = INT_TMR_SHARED;
#endif
tegra3_register_wake_timer(0);
#endif
*offset = TIMER1_OFFSET;
*irq = INT_TMR1;
}
static void __init tegra_init_timer(void)
{
struct clk *clk;
unsigned long rate = clk_measure_input_freq();
int ret;
clk = clk_get_sys("timer", NULL);
BUG_ON(IS_ERR(clk));
clk_enable(clk);
/*
* rtc registers are used by read_persistent_clock, keep the rtc clock
* enabled
*/
clk = clk_get_sys("rtc-tegra", NULL);
BUG_ON(IS_ERR(clk));
clk_enable(clk);
#ifdef CONFIG_HAVE_ARM_TWD
twd_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x600);
#endif
switch (rate) {
case 12000000:
timer_writel(0x000b, TIMERUS_USEC_CFG);
break;
case 13000000:
timer_writel(0x000c, TIMERUS_USEC_CFG);
break;
case 19200000:
timer_writel(0x045f, TIMERUS_USEC_CFG);
break;
case 26000000:
timer_writel(0x0019, TIMERUS_USEC_CFG);
break;
default:
WARN(1, "Unknown clock rate");
}
init_fixed_sched_clock(&cd, tegra_update_sched_clock, 32,
1000000, SC_MULT, SC_SHIFT);
if (clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
"timer_us", 1000000, 300, 32, clocksource_mmio_readl_up)) {
printk(KERN_ERR "Failed to register clocksource\n");
BUG();
}
ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq);
if (ret) {
printk(KERN_ERR "Failed to register timer IRQ: %d\n", ret);
BUG();
}
clockevents_calc_mult_shift(&tegra_clockevent, 1000000, 5);
tegra_clockevent.max_delta_ns =
clockevent_delta2ns(0x1fffffff, &tegra_clockevent);
tegra_clockevent.min_delta_ns =
clockevent_delta2ns(0x1, &tegra_clockevent);
tegra_clockevent.cpumask = cpu_all_mask;
tegra_clockevent.irq = tegra_timer_irq.irq;
clockevents_register_device(&tegra_clockevent);
}
void __init tegra_init_timer(struct device_node *np)
{
struct clk *clk;
int ret;
unsigned long rate;
struct resource res;
if (of_address_to_resource(np, 0, &res)) {
pr_err("%s:No memory resources found\n", __func__);
return;
}
timer_reg_base = ioremap(res.start, resource_size(&res));
if (!timer_reg_base) {
pr_err("%s:Can't map timer registers\n", __func__);
BUG();
}
timer_reg_base_pa = res.start;
tegra_timer_irq.irq = irq_of_parse_and_map(np, 0);
if (tegra_timer_irq.irq <= 0) {
pr_err("%s:Failed to map timer IRQ\n", __func__);
BUG();
}
clk = of_clk_get(np, 0);
if (IS_ERR(clk))
clk = clk_get_sys("timer", NULL);
if (IS_ERR(clk)) {
pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n");
rate = 12000000;
} else {
clk_prepare_enable(clk);
rate = clk_get_rate(clk);
}
switch (rate) {
case 12000000:
timer_writel(0x000b, TIMERUS_USEC_CFG);
break;
case 12800000:
timer_writel(0x043F, TIMERUS_USEC_CFG);
break;
case 13000000:
timer_writel(0x000c, TIMERUS_USEC_CFG);
break;
case 19200000:
timer_writel(0x045f, TIMERUS_USEC_CFG);
break;
case 26000000:
timer_writel(0x0019, TIMERUS_USEC_CFG);
break;
#ifndef CONFIG_ARCH_TEGRA_2x_SOC
case 16800000:
timer_writel(0x0453, TIMERUS_USEC_CFG);
break;
case 38400000:
timer_writel(0x04BF, TIMERUS_USEC_CFG);
break;
case 48000000:
timer_writel(0x002F, TIMERUS_USEC_CFG);
break;
#endif
default:
if (tegra_platform_is_qt()) {
timer_writel(0x000c, TIMERUS_USEC_CFG);
break;
}
WARN(1, "Unknown clock rate");
}
#ifdef CONFIG_PM_SLEEP
hotplug_cpu_register(np);
#endif
of_node_put(np);
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
tegra20_init_timer();
#else
tegra30_init_timer();
#endif
ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
"timer_us", 1000000, 300, 32,
clocksource_mmio_readl_up);
if (ret) {
pr_err("%s: Failed to register clocksource: %d\n",
__func__, ret);
BUG();
}
ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq);
if (ret) {
pr_err("%s: Failed to register timer IRQ: %d\n",
__func__, ret);
BUG();
}
clockevents_calc_mult_shift(&tegra_clockevent, 1000000, 5);
tegra_clockevent.max_delta_ns =
clockevent_delta2ns(0x1fffffff, &tegra_clockevent);
tegra_clockevent.min_delta_ns =
clockevent_delta2ns(0x1, &tegra_clockevent);
tegra_clockevent.cpumask = cpu_all_mask;
tegra_clockevent.irq = tegra_timer_irq.irq;
clockevents_register_device(&tegra_clockevent);
#ifndef CONFIG_ARM64
#ifdef CONFIG_ARM_ARCH_TIMER
/* Architectural timers take precedence over broadcast timers.
Only register a broadcast clockevent device if architectural
timers do not exist or cannot be initialized. */
if (tegra_init_arch_timer())
#endif
/* Architectural timers do not exist or cannot be initialzied.
Fall back to using the broadcast timer as the sched clock. */
setup_sched_clock(tegra_read_sched_clock, 32, 1000000);
#endif
register_syscore_ops(&tegra_timer_syscore_ops);
#ifndef CONFIG_ARM64
late_time_init = tegra_init_late_timer;
#endif
//arm_delay_ops.delay = __tegra_delay;
//arm_delay_ops.const_udelay = __tegra_const_udelay;
//arm_delay_ops.udelay = __tegra_udelay;
}
static void tegra_timer_resume(void)
{
timer_writel(usec_config, TIMERUS_USEC_CFG);
}
static irqreturn_t tegra_lp2wake_interrupt(int irq, void *dev_id)
{
timer_writel(1<<30, TIMER4_BASE + TIMER_PCR);
return IRQ_HANDLED;
}
static inline void timer_shutdown(struct clock_event_device *evt)
{
timer_writel(0, TIMER3_BASE + TIMER_PTV);
}
static void __init tegra20_init_timer(struct device_node *np)
{
struct clk *clk;
unsigned long rate;
int ret;
timer_reg_base = of_iomap(np, 0);
if (!timer_reg_base) {
pr_err("Can't map timer registers\n");
BUG();
}
tegra_timer_irq.irq = irq_of_parse_and_map(np, 2);
if (tegra_timer_irq.irq <= 0) {
pr_err("Failed to map timer IRQ\n");
BUG();
}
clk = of_clk_get(np, 0);
if (IS_ERR(clk)) {
pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n");
rate = 12000000;
} else {
clk_prepare_enable(clk);
rate = clk_get_rate(clk);
}
switch (rate) {
case 12000000:
timer_writel(0x000b, TIMERUS_USEC_CFG);
break;
case 13000000:
timer_writel(0x000c, TIMERUS_USEC_CFG);
break;
case 19200000:
timer_writel(0x045f, TIMERUS_USEC_CFG);
break;
case 26000000:
timer_writel(0x0019, TIMERUS_USEC_CFG);
break;
default:
WARN(1, "Unknown clock rate");
}
sched_clock_register(tegra_read_sched_clock, 32, 1000000);
if (clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
"timer_us", 1000000, 300, 32, clocksource_mmio_readl_up)) {
pr_err("Failed to register clocksource\n");
BUG();
}
ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq);
if (ret) {
pr_err("Failed to register timer IRQ: %d\n", ret);
BUG();
}
tegra_clockevent.cpumask = cpu_all_mask;
tegra_clockevent.irq = tegra_timer_irq.irq;
clockevents_config_and_register(&tegra_clockevent, 1000000,
0x1, 0x1fffffff);
}
void uemd_timer_init(void)
{
timer_writel(TIMER_RELOAD, TIMER_TIMER1LOAD);
timer_writel(TIMER_ENABLE | TIMER_SIZE32, TIMER_TIMER1CONTROL);
reset_timer_masked();
}
static void __init tegra20_init_timer(void)
{
struct device_node *np;
struct clk *clk;
unsigned long rate;
int ret;
np = of_find_matching_node(NULL, timer_match);
if (!np) {
pr_err("Failed to find timer DT node\n");
BUG();
}
timer_reg_base = of_iomap(np, 0);
if (!timer_reg_base) {
pr_err("Can't map timer registers\n");
BUG();
}
tegra_timer_irq.irq = irq_of_parse_and_map(np, 2);
if (tegra_timer_irq.irq <= 0) {
pr_err("Failed to map timer IRQ\n");
BUG();
}
clk = of_clk_get(np, 0);
if (IS_ERR(clk)) {
pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n");
rate = 12000000;
} else {
clk_prepare_enable(clk);
rate = clk_get_rate(clk);
}
of_node_put(np);
np = of_find_matching_node(NULL, rtc_match);
if (!np) {
pr_err("Failed to find RTC DT node\n");
BUG();
}
rtc_base = of_iomap(np, 0);
if (!rtc_base) {
pr_err("Can't map RTC registers");
BUG();
}
/*
* rtc registers are used by read_persistent_clock, keep the rtc clock
* enabled
*/
clk = of_clk_get(np, 0);
if (IS_ERR(clk))
pr_warn("Unable to get rtc-tegra clock\n");
else
clk_prepare_enable(clk);
of_node_put(np);
switch (rate) {
case 12000000:
timer_writel(0x000b, TIMERUS_USEC_CFG);
break;
case 13000000:
timer_writel(0x000c, TIMERUS_USEC_CFG);
break;
case 19200000:
timer_writel(0x045f, TIMERUS_USEC_CFG);
break;
case 26000000:
timer_writel(0x0019, TIMERUS_USEC_CFG);
break;
default:
WARN(1, "Unknown clock rate");
}
setup_sched_clock(tegra_read_sched_clock, 32, 1000000);
if (clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
"timer_us", 1000000, 300, 32, clocksource_mmio_readl_up)) {
pr_err("Failed to register clocksource\n");
BUG();
}
ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq);
if (ret) {
pr_err("Failed to register timer IRQ: %d\n", ret);
BUG();
}
tegra_clockevent.cpumask = cpu_all_mask;
tegra_clockevent.irq = tegra_timer_irq.irq;
clockevents_config_and_register(&tegra_clockevent, 1000000,
0x1, 0x1fffffff);
#ifdef CONFIG_HAVE_ARM_TWD
twd_local_timer_of_register();
#endif
register_persistent_clock(NULL, tegra_read_persistent_clock);
}
