/* Set the clock rate for a clock source */
int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
{
int ret = -EINVAL;
pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate);
/* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
if (clk->set_rate) {
trace_clock_set_rate(clk->name, rate, smp_processor_id());
ret = clk->set_rate(clk, rate);
}
return ret;
}
int clk_set_rate(struct clk *clk, unsigned long rate)
{
unsigned long start_rate, flags;
int rc;
if (IS_ERR_OR_NULL(clk))
return -EINVAL;
if (!clk->ops->set_rate)
return -ENOSYS;
spin_lock_irqsave(&clk->lock, flags);
trace_clock_set_rate(clk->dbg_name, rate, smp_processor_id());
if (clk->count) {
start_rate = clk->rate;
/* Enforce vdd requirements for target frequency. */
rc = vote_rate_vdd(clk, rate);
if (rc)
goto err_vote_vdd;
rc = clk->ops->set_rate(clk, rate);
if (rc)
goto err_set_rate;
/* Release vdd requirements for starting frequency. */
unvote_rate_vdd(clk, start_rate);
} else {
rc = clk->ops->set_rate(clk, rate);
}
if (!rc)
clk->rate = rate;
spin_unlock_irqrestore(&clk->lock, flags);
return rc;
err_set_rate:
unvote_rate_vdd(clk, rate);
err_vote_vdd:
spin_unlock_irqrestore(&clk->lock, flags);
return rc;
}
