static void zstencil_clear(struct brw_context *brw,
struct brw_surface *bsurface,
unsigned clear_flags,
double depth,
unsigned stencil )
{
enum pipe_error ret;
unsigned value;
unsigned mask = 0;
union fi tmp;
if (clear_flags & PIPE_CLEAR_DEPTH)
mask |= XY_BLT_WRITE_RGB;
switch (bsurface->base.format) {
case PIPE_FORMAT_Z32_FLOAT:
tmp.f = (float)depth;
value = tmp.ui;
break;
case PIPE_FORMAT_Z24X8_UNORM:
case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
value = ((unsigned)(depth * MASK24) & MASK24);
break;
case PIPE_FORMAT_Z16_UNORM:
value = ((unsigned)(depth * MASK16) & MASK16);
break;
default:
assert(0);
return;
}
switch (bsurface->base.format) {
case PIPE_FORMAT_Z32_FLOAT:
mask |= XY_BLT_WRITE_ALPHA;
break;
case PIPE_FORMAT_Z24X8_UNORM:
value = value | (stencil << 24);
mask |= XY_BLT_WRITE_ALPHA;
break;
case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
value = value | (stencil << 24);
if (clear_flags & PIPE_CLEAR_STENCIL)
mask |= XY_BLT_WRITE_ALPHA;
break;
case PIPE_FORMAT_Z16_UNORM:
value = value | (value << 16);
mask |= XY_BLT_WRITE_ALPHA;
break;
default:
break;
}
ret = try_clear( brw, bsurface, value, mask );
if (ret != 0) {
brw_context_flush( brw );
ret = try_clear( brw, bsurface, value, mask );
assert( ret == 0 );
}
}
/**
* Clear the given surface to the specified value.
* No masking, no scissor (clear entire buffer).
*/
void
svga_clear(struct pipe_context *pipe, unsigned buffers, const float *rgba,
double depth, unsigned stencil)
{
struct svga_context *svga = svga_context( pipe );
int ret;
if (buffers & PIPE_CLEAR_COLOR)
SVGA_DBG(DEBUG_DMA, "clear sid %p\n",
svga_surface(svga->curr.framebuffer.cbufs[0])->handle);
ret = try_clear( svga, buffers, rgba, depth, stencil );
if (ret == PIPE_ERROR_OUT_OF_MEMORY) {
/* Flush command buffer and retry:
*/
svga_context_flush( svga, NULL );
ret = try_clear( svga, buffers, rgba, depth, stencil );
}
/*
* Mark target surfaces as dirty
* TODO Mark only cleared surfaces.
*/
svga_mark_surfaces_dirty(svga);
assert (ret == PIPE_OK);
}
/**
* Clear the given surface to the specified value.
* No masking, no scissor (clear entire buffer).
*/
void
svga_clear(struct pipe_context *pipe, unsigned buffers,
const union pipe_color_union *color,
double depth, unsigned stencil)
{
struct svga_context *svga = svga_context( pipe );
enum pipe_error ret;
if (buffers & PIPE_CLEAR_COLOR)
SVGA_DBG(DEBUG_DMA, "clear sid %p\n",
svga_surface(svga->curr.framebuffer.cbufs[0])->handle);
/* flush any queued prims (don't want them to appear after the clear!) */
svga_hwtnl_flush_retry(svga);
ret = try_clear( svga, buffers, color, depth, stencil );
if (ret == PIPE_ERROR_OUT_OF_MEMORY) {
/* Flush command buffer and retry:
*/
svga_context_flush( svga, NULL );
ret = try_clear( svga, buffers, color, depth, stencil );
}
/*
* Mark target surfaces as dirty
* TODO Mark only cleared surfaces.
*/
svga_mark_surfaces_dirty(svga);
assert (ret == PIPE_OK);
}
static void color_clear(struct brw_context *brw,
struct brw_surface *bsurface,
const float *rgba )
{
enum pipe_error ret;
union util_color value;
util_pack_color( rgba, bsurface->base.format, &value );
if (bsurface->cpp == 2)
value.ui |= value.ui << 16;
ret = try_clear( brw, bsurface, value.ui,
XY_BLT_WRITE_RGB | XY_BLT_WRITE_ALPHA );
if (ret != 0) {
brw_context_flush( brw );
ret = try_clear( brw, bsurface, value.ui,
XY_BLT_WRITE_RGB | XY_BLT_WRITE_ALPHA );
assert( ret == 0 );
}
}
