static int hub_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *codec_dai = rtd->codec_dai;
struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
int ret;
DBG("\n");
// McBSP2 SLAVE MODE mux settings
omap_mux_init_signal("mcbsp2_fsx.mcbsp2_fsx",OMAP_PIN_INPUT);
omap_mux_init_signal("mcbsp2_clkx.mcbsp2_clkx",OMAP_PIN_INPUT);
omap_mux_init_signal("mcbsp2_dr.mcbsp2_dr",OMAP_PIN_INPUT);
omap_mux_init_signal("mcbsp2_dx.mcbsp2_dx",OMAP_PIN_OUTPUT | OMAP_PULL_ENA);
#if OMAP_MCBSP_MASTER_MODE
struct snd_soc_dai *codec_dai = rtd->dai->codec_dai;
int divisor;
// omap3_mux_config("OMAP_MCBSP3_MASTER");
omap_mux_init_signal("mcbsp_clks.mcbsp_clks",OMAP_PIN_INPUT);
omap_mux_init_signal("mcbsp3_fsx.mcbsp3_fsx",OMAP_PIN_OUTPUT);
omap_mux_init_signal("mcbsp3_clkx.mcbsp3_clkx",OMAP_PIN_OUTPUT);
omap_mux_init_signal("mcbsp3_dr.mcbsp3_dr",OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("mcbsp3_dx.mcbsp3_dx",OMAP_PIN_OUTPUT);
/* Set codec DAI configuration */
ret = snd_soc_dai_set_fmt(codec_dai,
SND_SOC_DAIFMT_DSP_B |
SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS);
if (ret < 0) {
printk(KERN_ERR "can't set codec DAI configuration\n");
return ret;
}
/* Set cpu DAI configuration */
ret = snd_soc_dai_set_fmt(cpu_dai,
SND_SOC_DAIFMT_DSP_B |
SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS);
if (ret < 0) {
printk(KERN_ERR "can't set cpu DAI configuration\n");
return ret;
}
/* Set the codec system clock for DAC and ADC */
ret = snd_soc_dai_set_sysclk(codec_dai, 0, 26000000,
SND_SOC_CLOCK_IN);
if (ret < 0) {
printk(KERN_ERR "can't set codec system clock\n");
return ret;
}
ret = twl4030_set_rate(codec_dai->codec, params);
/* Use external (CLK256FS) clock for mcBSP3 */
ret = snd_soc_dai_set_sysclk(cpu_dai, OMAP_MCBSP_SYSCLK_CLKS_EXT,
0, SND_SOC_CLOCK_OUT);
if (ret < 0) {
printk(KERN_ERR "can't set mcBSP3 to external clock\n");
return ret;
}
divisor = twl4030_get_clock_divisor(codec_dai->codec, params);
ret = snd_soc_dai_set_clkdiv(cpu_dai, OMAP_MCBSP_CLKGDV, divisor);
if (ret < 0) {
printk(KERN_ERR "can't set codec clock divisor\n");
return ret;
}
#else
// omap3_mux_config("OMAP_MCBSP3_SLAVE");
omap_mux_init_signal("mcbsp3_fsx.mcbsp3_fsx",OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("mcbsp3_clkx.mcbsp3_clkx",OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("mcbsp3_dr.mcbsp3_dr",OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("mcbsp3_dx.mcbsp3_dx",OMAP_PIN_OUTPUT);
/* Set cpu DAI configuration */
ret = snd_soc_dai_set_fmt(cpu_dai,
SND_SOC_DAIFMT_DSP_B |
SND_SOC_DAIFMT_IB_IF |
SND_SOC_DAIFMT_CBM_CFM);
if (ret < 0) {
printk(KERN_ERR "can't set cpu DAI configuration\n");
return ret;
}
#endif
return 0;
}
static int hub_fm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *cpu_dai = rtd->cpu_dai; // 20110106 [email protected]
int ret;
DBG("\n");
#if OMAP_MCBSP_MASTER_MODE
struct snd_soc_dai *codec_dai = rtd->dai->codec_dai;
int divisor;
/* Set codec DAI configuration */
ret = snd_soc_dai_set_fmt(codec_dai,
SND_SOC_DAIFMT_I2S |
SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS);
if (ret < 0) {
printk(KERN_ERR "can't set codec DAI configuration\n");
return ret;
}
/* Set cpu DAI configuration */
ret = snd_soc_dai_set_fmt(cpu_dai,
SND_SOC_DAIFMT_I2S |
SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS);
if (ret < 0) {
printk(KERN_ERR "can't set cpu DAI configuration\n");
return ret;
}
/* Set the codec system clock for DAC and ADC */
ret = snd_soc_dai_set_sysclk(codec_dai, 0, 26000000,
SND_SOC_CLOCK_IN);
if (ret < 0) {
printk(KERN_ERR "can't set codec system clock\n");
return ret;
}
ret = twl4030_set_rate(codec_dai->codec, params);
/* Use external (CLK256FS) clock for mcBSP4 */
ret = snd_soc_dai_set_sysclk(cpu_dai, OMAP_MCBSP_SYSCLK_CLKS_EXT,
0, SND_SOC_CLOCK_OUT);
if (ret < 0) {
printk(KERN_ERR "can't set mcBSP4 to external clock\n");
return ret;
}
divisor = twl4030_get_clock_divisor(codec_dai->codec, params);
ret = snd_soc_dai_set_clkdiv(cpu_dai, OMAP_MCBSP_CLKGDV, divisor);
if (ret < 0) {
printk(KERN_ERR "can't set codec clock divisor\n");
return ret;
}
#else
/* Set cpu DAI configuration */
ret = snd_soc_dai_set_fmt(cpu_dai,
SND_SOC_DAIFMT_I2S |
SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBM_CFM);
if (ret < 0) {
printk(KERN_ERR "can't set cpu DAI configuration\n");
return ret;
}
#endif
return 0;
}
static int hub_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *codec_dai = rtd->codec_dai;
struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
int ret;
DBG("\n");
#if OMAP_MCBSP_MASTER_MODE
struct snd_soc_dai *codec_dai = rtd->dai->codec_dai;
int divisor;
// omap3_mux_config("OMAP_MCBSP3_MASTER");
omap_mux_init_signal("mcbsp_clks.mcbsp_clks",OMAP_PIN_INPUT);
omap_mux_init_signal("mcbsp3_fsx.mcbsp3_fsx",OMAP_PIN_OUTPUT);
omap_mux_init_signal("mcbsp3_clkx.mcbsp3_clkx",OMAP_PIN_OUTPUT);
omap_mux_init_signal("mcbsp3_dr.mcbsp3_dr",OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("mcbsp3_dx.mcbsp3_dx",OMAP_PIN_OUTPUT);
/* Set codec DAI configuration */
ret = snd_soc_dai_set_fmt(codec_dai,
SND_SOC_DAIFMT_DSP_B |
SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS);
if (ret < 0) {
printk(KERN_ERR "can't set codec DAI configuration\n");
return ret;
}
/* Set cpu DAI configuration */
ret = snd_soc_dai_set_fmt(cpu_dai,
SND_SOC_DAIFMT_DSP_B |
SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS);
if (ret < 0) {
printk(KERN_ERR "can't set cpu DAI configuration\n");
return ret;
}
/* Set the codec system clock for DAC and ADC */
ret = snd_soc_dai_set_sysclk(codec_dai, 0, 26000000,
SND_SOC_CLOCK_IN);
if (ret < 0) {
printk(KERN_ERR "can't set codec system clock\n");
return ret;
}
ret = twl4030_set_rate(codec_dai->codec, params);
/* Use external (CLK256FS) clock for mcBSP3 */
ret = snd_soc_dai_set_sysclk(cpu_dai, OMAP_MCBSP_SYSCLK_CLKS_EXT,
0, SND_SOC_CLOCK_OUT);
if (ret < 0) {
printk(KERN_ERR "can't set mcBSP3 to external clock\n");
return ret;
}
divisor = twl4030_get_clock_divisor(codec_dai->codec, params);
ret = snd_soc_dai_set_clkdiv(cpu_dai, OMAP_MCBSP_CLKGDV, divisor);
if (ret < 0) {
printk(KERN_ERR "can't set codec clock divisor\n");
return ret;
}
#else
if (pcm_hw_enable==1)
return 0;
// omap3_mux_config("OMAP_MCBSP3_SLAVE");
omap_mux_init_signal("mcbsp3_fsx.mcbsp3_fsx",OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("mcbsp3_clkx.mcbsp3_clkx",OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("mcbsp3_dr.mcbsp3_dr",OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("mcbsp3_dx.mcbsp3_dx",OMAP_PIN_OUTPUT);
/* Set cpu DAI configuration */
ret = snd_soc_dai_set_fmt(cpu_dai,
SND_SOC_DAIFMT_DSP_B |
SND_SOC_DAIFMT_IB_IF |
SND_SOC_DAIFMT_CBM_CFM);
if (ret < 0) {
printk(KERN_ERR "can't set cpu DAI configuration\n");
return ret;
}
if (pcm_hw_enable==0)
{
pcm_hw_enable=1;
DBG("cur_voice_mode=%d \n",cur_voice_mode);
#if 1//20110126 jisun.kwon : need to merge
voice_configure_path(cur_voice_mode);
if (cur_voice_mode ==TWL4030_VT_SPEAKER_CALL_MODE)
{
wm9093_configure_path(5);
}
else if (cur_voice_mode ==TWL4030_VT_HEADSET_CALL_MODE)
{
wm9093_configure_path(6);
}
else
{
}
#endif
}
#endif
return 0;
}