int main() {
int n;
short vref = *(short*)((void*)0x1FFFF7BA);
REG_L(RCC_BASE, RCC_AHBENR) |= (1 << 17); // port A clock
REG_L(RCC_BASE, RCC_AHB2ENR) |= (1 << 9); // ADC clock
REG_L(GPIOA_BASE, GPIO_MODER) |= 1;
uartEnable();
adcEnable();
REG_L(ADC_BASE, ADC_CHSELR) |= (1 << 5); // ADC from PA5
REG_L(ADC_BASE, ADC_CHSELR) |= (1 << 17); // ADC from vrefint
while(1) {
REG_L(GPIOA_BASE, GPIO_BSRR) |= (1 << 0);
sends("on\n");
adcRead(2);
sends("adc=0x");
sendHex(adc[0], 3);
n = (intDiv(3300 * (int) adc[0], adc[1]) * vref) >> 12;
sends(", V=");
sendDec(n);
sends("mv, T=");
sendDec(intDiv(((n - 2980) + 5), 10) + 25);
sends("\n");
n=250000; while(--n);
REG_L(GPIOA_BASE, GPIO_BSRR) |= (1 << 16);
sends("off\n");
n=1000000; while(--n);
}
}
static BT_ERROR uartSetBaudrate(BT_HANDLE hUart, BT_u32 ulBaudrate) {
volatile LM3Sxx_UART_REGS *pRegs = hUart->pRegs;
BT_u32 ulInputClk;
BT_u32 BaudRate = ulBaudrate;
/*
* We must determine the input clock frequency to the UART peripheral.
*/
ulInputClk = BT_LM3Sxx_GetSystemFrequency();
uartDisable(hUart);
/*
* Determine the Baud divider. It can be 4to 254.
* Loop through all possible combinations
*/
// Is the required baud rate greater than the maximum rate supported
// without the use of high speed mode?
if((BaudRate * 16) > ulInputClk) {
// Enable high speed mode.
pRegs->CTL |= LM3Sxx_UART_CTL_HSE;
// Half the supplied baud rate to compensate for enabling high speed
// mode. This allows the following code to be common to both cases.
BaudRate /= 2;
}
else {
// Disable high speed mode.
pRegs->CTL &= ~(LM3Sxx_UART_CTL_HSE);
}
// Compute the fractional baud rate divider.
BT_u32 ulDiv = (((ulInputClk * 8) / BaudRate) + 1) / 2;
// Set the baud rate.
pRegs->IBRD = ulDiv / 64;
pRegs->FBRD = ulDiv % 64;
// Start the UART.
uartEnable(hUart);
return BT_ERR_NONE;
}
/**
* Complete a full configuration of the UART.
**/
static BT_ERROR uartSetConfig(BT_HANDLE hUart, BT_UART_CONFIG *pConfig) {
volatile LM3Sxx_UART_REGS *pRegs = hUart->pRegs;
BT_ERROR Error = BT_ERR_NONE;
uartSetBaudrate(hUart, pConfig->ulBaudrate);
uartDisable(hUart);
// Set parity, data length, and number of stop bits.
pRegs->LCRH = (pConfig->ucDataBits - 5) << 5;
pRegs->LCRH |= (pConfig->ucStopBits) << 3;
if (pConfig->ucParity == BT_UART_PARITY_ODD) pRegs->LCRH |= LM3Sxx_UART_LCRH_ODD;
if (pConfig->ucParity == BT_UART_PARITY_EVEN) pRegs->LCRH |= LM3Sxx_UART_LCRH_EVEN;
if (pConfig->ucParity == BT_UART_PARITY_MARK) pRegs->LCRH |= LM3Sxx_UART_LCRH_MARK;
if (pConfig->ucParity == BT_UART_PARITY_SPACE) pRegs->LCRH |= LM3Sxx_UART_LCRH_SPACE;
// Clear the flags register.
pRegs->FR = 0;
uartEnable(hUart);
switch(pConfig->eMode) {
case BT_UART_MODE_POLLED: {
if(hUart->eMode != BT_UART_MODE_POLLED) {
if(hUart->hTxFifo) {
BT_CloseHandle(hUart->hTxFifo);
hUart->hTxFifo = NULL;
}
if(hUart->hRxFifo) {
BT_CloseHandle(hUart->hRxFifo);
hUart->hRxFifo = NULL;
}
// Disable TX and RX interrupts
pRegs->IM &= ~(LM3Sxx_UART_INT_RX | LM3Sxx_UART_INT_RT); // Disable the interrupt
hUart->eMode = BT_UART_MODE_POLLED;
}
break;
}
case BT_UART_MODE_BUFFERED:
{
if(hUart->eMode != BT_UART_MODE_BUFFERED) {
if(!hUart->hRxFifo && !hUart->hTxFifo) {
hUart->hRxFifo = BT_FifoCreate(pConfig->ulRxBufferSize, 1, 0, &Error);
hUart->hTxFifo = BT_FifoCreate(pConfig->ulTxBufferSize, 1, 0, &Error);
pRegs->IM |= LM3Sxx_UART_INT_RX | LM3Sxx_UART_INT_RT; // Enable the interrupt
hUart->eMode = BT_UART_MODE_BUFFERED;
}
}
break;
}
default:
// Unsupported operating mode!
break;
}
return BT_ERR_NONE;
}
