static uint64_t uart_read(void *opaque, hwaddr addr,
unsigned int size)
{
AlteraUART *s = opaque;
uint32_t r = 0;
addr >>= 2;
addr &= 0x7;
switch (addr) {
case R_RXDATA:
r = s->regs[R_RXDATA];
s->regs[R_STATUS] &= ~STATUS_RRDY;
uart_update_irq(s);
break;
case R_STATUS:
r = s->regs[R_STATUS];
s->regs[R_STATUS] &= ~(STATUS_PE | STATUS_FE | STATUS_BRK |
STATUS_ROE | STATUS_TOE | STATUS_E |
STATUS_DTCS);
uart_update_irq(s);
break;
default:
if (addr < ARRAY_SIZE(s->regs)) {
r = s->regs[addr];
}
break;
}
return r;
}
static void uart_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
LM32UartState *s = opaque;
unsigned char ch = value;
trace_lm32_uart_memory_write(addr, value);
addr >>= 2;
switch (addr) {
case R_RXTX:
if (s->chr) {
qemu_chr_fe_write(s->chr, &ch, 1);
}
break;
case R_IER:
case R_LCR:
case R_MCR:
case R_DIV:
s->regs[addr] = value;
break;
case R_IIR:
case R_LSR:
case R_MSR:
error_report("lm32_uart: write access to read only register 0x"
TARGET_FMT_plx, addr << 2);
break;
default:
error_report("lm32_uart: write access to unknown register 0x"
TARGET_FMT_plx, addr << 2);
break;
}
uart_update_irq(s);
}
static uint64_t uart_read(void *opaque, hwaddr addr,
unsigned size)
{
LM32UartState *s = opaque;
uint32_t r = 0;
addr >>= 2;
switch (addr) {
case R_RXTX:
r = s->regs[R_RXTX];
s->regs[R_LSR] &= ~LSR_DR;
uart_update_irq(s);
qemu_chr_accept_input(s->chr);
break;
case R_IIR:
case R_LSR:
case R_MSR:
r = s->regs[addr];
break;
case R_IER:
case R_LCR:
case R_MCR:
case R_DIV:
error_report("lm32_uart: read access to write only register 0x"
TARGET_FMT_plx, addr << 2);
break;
default:
error_report("lm32_uart: read access to unknown register 0x"
TARGET_FMT_plx, addr << 2);
break;
}
trace_lm32_uart_memory_read(addr << 2, r);
return r;
}
static uint64_t
uart_read(void *opaque, hwaddr addr, unsigned int size)
{
struct xlx_uartlite *s = opaque;
uint32_t r = 0;
addr >>= 2;
switch (addr)
{
case R_RX:
r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 7];
if (s->rx_fifo_len)
s->rx_fifo_len--;
uart_update_status(s);
uart_update_irq(s);
qemu_chr_accept_input(s->chr);
break;
default:
if (addr < ARRAY_SIZE(s->regs))
r = s->regs[addr];
DUART(qemu_log("%s addr=%x v=%x\n", __func__, addr, r));
break;
}
return r;
}
static void uart_write(void *opaque, target_phys_addr_t addr, uint64_t value,
unsigned size)
{
MilkymistUartState *s = opaque;
unsigned char ch = value;
trace_milkymist_uart_memory_write(addr, value);
addr >>= 2;
switch (addr) {
case R_RXTX:
if (s->chr) {
qemu_chr_fe_write(s->chr, &ch, 1);
}
s->regs[R_STAT] |= STAT_TX_EVT;
break;
case R_DIV:
case R_CTRL:
case R_DBG:
s->regs[addr] = value;
break;
case R_STAT:
/* write one to clear bits */
s->regs[addr] &= ~(value & (STAT_RX_EVT | STAT_TX_EVT));
break;
default:
error_report("milkymist_uart: write access to unknown register 0x"
TARGET_FMT_plx, addr << 2);
break;
}
uart_update_irq(s);
}
static void uart_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
{
AlteraUART *s = opaque;
uint32_t value = val64;
unsigned char ch = value;
addr >>= 2;
addr &= 0x7;
switch (addr) {
case R_TXDATA:
if (s->chr) {
qemu_chr_fe_write(s->chr, &ch, 1);
}
s->regs[addr] = value;
break;
case R_RXDATA:
case R_STATUS:
/* No writeable bits */
break;
default:
s->regs[addr] = value;
break;
}
uart_update_irq(s);
}
static void uart_rx(void *opaque, const uint8_t *buf, int size)
{
AlteraUART *s = opaque;
s->regs[R_RXDATA] = *buf;
s->regs[R_STATUS] |= STATUS_RRDY;
uart_update_irq(s);
}
static void uart_rx(void *opaque, const uint8_t *buf, int size)
{
MilkymistUartState *s = opaque;
assert(!(s->regs[R_STAT] & STAT_RX_EVT));
s->regs[R_STAT] |= STAT_RX_EVT;
s->regs[R_RXTX] = *buf;
uart_update_irq(s);
}
static void uart_rx(void *opaque, const uint8_t *buf, int size)
{
LM32UartState *s = opaque;
if (s->regs[R_LSR] & LSR_DR) {
s->regs[R_LSR] |= LSR_OE;
}
s->regs[R_LSR] |= LSR_DR;
s->regs[R_RXTX] = *buf;
uart_update_irq(s);
}
static void uart_rx(void *opaque, const uint8_t *buf, int size)
{
struct xlx_uartlite *s = opaque;
/* Got a byte. */
if (s->rx_fifo_len >= 8) {
printf("WARNING: UART dropped char.\n");
return;
}
s->rx_fifo[s->rx_fifo_pos] = *buf;
s->rx_fifo_pos++;
s->rx_fifo_pos &= 0x7;
s->rx_fifo_len++;
uart_update_status(s);
uart_update_irq(s);
}
static void
uart_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
{
struct xlx_uartlite *s = opaque;
uint32_t value = val64;
unsigned char ch = value;
addr >>= 2;
switch (addr)
{
case R_STATUS:
hw_error("write to UART STATUS?\n");
break;
case R_CTRL:
if (value & CONTROL_RST_RX) {
s->rx_fifo_pos = 0;
s->rx_fifo_len = 0;
}
s->regs[addr] = value;
break;
case R_TX:
if (s->chr)
qemu_chr_fe_write(s->chr, &ch, 1);
s->regs[addr] = value;
/* hax. */
s->regs[R_STATUS] |= STATUS_IE;
break;
default:
DUART(printf("%s addr=%x v=%x\n", __func__, addr, value));
if (addr < ARRAY_SIZE(s->regs))
s->regs[addr] = value;
break;
}
uart_update_status(s);
uart_update_irq(s);
}
static uint32_t uart_readl (void *opaque, target_phys_addr_t addr)
{
struct xlx_uartlite *s = opaque;
uint32_t r = 0;
addr >>= 2;
switch (addr)
{
case R_RX:
r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 7];
if (s->rx_fifo_len)
s->rx_fifo_len--;
uart_update_status(s);
uart_update_irq(s);
break;
default:
if (addr < ARRAY_SIZE(s->regs))
r = s->regs[addr];
DUART(qemu_log("%s addr=%x v=%x\n", __func__, addr, r));
break;
}
return r;
}
