static void udacodec_reset(void)
{
/* uda reset */
l3_init();
udacodec_write (UDA_REG_STATUS, UDA_STATUS_0 | UDA_RESET | UDA_SYSCLK_256FS |
I2S_IFMT_IIS);
udacodec_write (UDA_REG_STATUS, UDA_STATUS_0 | UDA_SYSCLK_256FS | I2S_IFMT_IIS);
udacodec_write (UDA_REG_STATUS, UDA_STATUS_1 | UDA_POWER_DAC_ON);
uda_regs[UDA_REG_ID_CTRL2] = UDA_PEAK_DETECT_POS_AFTER |
UDA_DE_EMPHASIS_NONE | UDA_MUTE_OFF | UDA_MODE_SWITCH_FLAT;
}
void audiohw_set_treble(int value)
{
uda_regs [UDA_REG_ID_CTRL1] &= UDA_TREBLE (UDA_TREBLE_MASK);
uda_regs [UDA_REG_ID_CTRL1] |= UDA_TREBLE (value & UDA_TREBLE_MASK);
udacodec_write (UDA_REG_DATA0, UDA_DATA_CTRL1 | uda_regs [UDA_REG_ID_CTRL1] );
}
void audiohw_set_bass(int value)
{
uda_regs [UDA_REG_ID_CTRL1] &= UDA_BASS_BOOST (UDA_BASS_BOOST_MASK);
uda_regs [UDA_REG_ID_CTRL1] |= UDA_BASS_BOOST (value & UDA_BASS_BOOST_MASK);
udacodec_write (UDA_REG_DATA0, UDA_DATA_CTRL1 | uda_regs [UDA_REG_ID_CTRL1] );
}
/* Returns 0 if register was written or -1 if write failed */
static int uda1380_write_reg(unsigned char reg, unsigned short value)
{
if (udacodec_write(reg, value) < 0)
{
DEBUGF("uda1380 error reg=0x%x", reg);
return -1;
}
uda1380_regs[reg] = value;
return 0;
}
void audiohw_close(void)
{
/* DAC, ADC off */
udacodec_write (UDA_REG_STATUS, UDA_STATUS_1 | 0);
}
