static void pca100_usb_register(void)
{
mdelay(10);
gpio_direction_output(GPIO_PORTB + 24, 0);
gpio_direction_output(GPIO_PORTB + 23, 0);
mdelay(10);
ulpi_setup((void *)(MX27_USB_OTG_BASE_ADDR + 0x170), 1);
add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX27_USB_OTG_BASE_ADDR, NULL);
ulpi_setup((void *)(MX27_USB_OTG_BASE_ADDR + 0x570), 1);
add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX27_USB_OTG_BASE_ADDR + 0x400, NULL);
}
static int imx_chipidea_port_init(void *drvdata)
{
struct imx_chipidea *ci = drvdata;
int ret;
if ((ci->flags & MXC_EHCI_PORTSC_MASK) == MXC_EHCI_MODE_ULPI) {
dev_dbg(ci->dev, "using ULPI phy\n");
if (IS_ENABLED(CONFIG_USB_ULPI)) {
ret = ulpi_setup(ci->base + 0x170, 1);
if (ret)
dev_err(ci->dev, "ULPI setup failed with %s\n",
strerror(-ret));
mdelay(20);
} else {
dev_err(ci->dev, "no ULPI support available\n");
ret = -ENODEV;
}
if (ret)
return ret;
}
ret = imx_usbmisc_port_init(ci->portno, ci->flags);
if (ret)
dev_err(ci->dev, "misc init failed: %s\n", strerror(-ret));
return ret;
}
static int imx_chipidea_probe(struct device_d *dev)
{
struct imxusb_platformdata *pdata = dev->platform_data;
int ret;
void __iomem *base;
struct ehci_data data = {};
uint32_t portsc;
if (!pdata) {
dev_err(dev, "no pdata!\n");
return -EINVAL;
}
base = dev_request_mem_region(dev, 0);
if (!base)
return -ENODEV;
data.init = imx_chipidea_port_init;
data.post_init = imx_chipidea_port_post_init;
data.drvdata = dev;
portsc = readl(base + 0x184);
portsc &= ~MXC_EHCI_PORTSC_MASK;
portsc |= pdata->flags & MXC_EHCI_PORTSC_MASK;
writel(portsc, base + 0x184);
imx_chipidea_port_init(dev);
if ((pdata->flags & MXC_EHCI_PORTSC_MASK) == MXC_EHCI_MODE_ULPI) {
dev_dbg(dev, "using ULPI phy\n");
if (IS_ENABLED(CONFIG_USB_ULPI)) {
ret = ulpi_setup(base + 0x170, 1);
} else {
dev_err(dev, "no ULPI support available\n");
ret = -ENODEV;
}
if (ret)
return ret;
}
data.hccr = base + 0x100;
data.hcor = base + 0x140;
data.flags = EHCI_HAS_TT;
if (pdata->mode == IMX_USB_MODE_HOST && IS_ENABLED(CONFIG_USB_EHCI)) {
ret = ehci_register(dev, &data);
} else if (pdata->mode == IMX_USB_MODE_DEVICE && IS_ENABLED(CONFIG_USB_GADGET_DRIVER_ARC)) {
ret = ci_udc_register(dev, base);
} else {
dev_err(dev, "No supported role\n");
ret = -ENODEV;
}
return ret;
};
static void neso_usbh_init(void)
{
uint32_t temp;
temp = readl(MX27_USB_OTG_BASE_ADDR + 0x600);
temp &= ~((3 << 21) | 1);
temp |= (1 << 5) | (1 << 16) | (1 << 19) | (1 << 20) | (1<<11);
writel(temp, MX27_USB_OTG_BASE_ADDR + 0x600);
temp = readl(MX27_USB_OTG_BASE_ADDR + 0x584);
temp &= ~(3 << 30);
temp |= 2 << 30;
writel(temp, MX27_USB_OTG_BASE_ADDR + 0x584);
mdelay(10);
gpio_set_value(USBH2_PHY_CS_GPIO, 0);
mdelay(10);
ulpi_setup((void *)(MX27_USB_OTG_BASE_ADDR + 0x570), 1);
}
static void pcm037_usb_init(void)
{
u32 tmp;
/* enable clock */
tmp = readl(0x53f80000);
tmp |= (1 << 9);
writel(tmp, 0x53f80000);
/* Host 1 */
tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x600);
tmp &= ~((3 << 21) | 1);
tmp |= (1 << 5) | (1 << 16) | (1 << 19) | (1 << 11) | (1 << 20);
writel(tmp, MX31_USB_OTG_BASE_ADDR + 0x600);
tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x184);
tmp &= ~(3 << 30);
tmp |= 2 << 30;
writel(tmp, MX31_USB_OTG_BASE_ADDR + 0x184);
imx_iomux_mode(MX31_PIN_USBOTG_DATA0__USBOTG_DATA0);
imx_iomux_mode(MX31_PIN_USBOTG_DATA1__USBOTG_DATA1);
imx_iomux_mode(MX31_PIN_USBOTG_DATA2__USBOTG_DATA2);
imx_iomux_mode(MX31_PIN_USBOTG_DATA3__USBOTG_DATA3);
imx_iomux_mode(MX31_PIN_USBOTG_DATA4__USBOTG_DATA4);
imx_iomux_mode(MX31_PIN_USBOTG_DATA5__USBOTG_DATA5);
imx_iomux_mode(MX31_PIN_USBOTG_DATA6__USBOTG_DATA6);
imx_iomux_mode(MX31_PIN_USBOTG_DATA7__USBOTG_DATA7);
imx_iomux_mode(MX31_PIN_USBOTG_CLK__USBOTG_CLK);
imx_iomux_mode(MX31_PIN_USBOTG_DIR__USBOTG_DIR);
imx_iomux_mode(MX31_PIN_USBOTG_NXT__USBOTG_NXT);
imx_iomux_mode(MX31_PIN_USBOTG_STP__USBOTG_STP);
mdelay(50);
ulpi_setup((void *)(MX31_USB_OTG_BASE_ADDR + 0x170), 1);
/* Host 2 */
tmp = readl(MX31_IOMUXC_GPR);
tmp |= 1 << 11; /* IOMUX GPR: enable USBH2 signals */
writel(tmp, MX31_IOMUXC_GPR);
imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC));
imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC));
imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC));
imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC));
imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC));
imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC));
imx_iomux_mode(IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC));
imx_iomux_mode(IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC));
imx_iomux_mode(IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC));
imx_iomux_mode(IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC));
imx_iomux_mode(IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC));
imx_iomux_mode(IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC));
#define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
imx_iomux_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG);
imx_iomux_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG);
imx_iomux_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG);
imx_iomux_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG);
imx_iomux_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */
imx_iomux_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */
imx_iomux_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG); /* USBH2_DATA2 */
imx_iomux_set_pad(MX31_PIN_STXD6, H2_PAD_CFG); /* USBH2_DATA3 */
imx_iomux_set_pad(MX31_PIN_SFS3, H2_PAD_CFG); /* USBH2_DATA4 */
imx_iomux_set_pad(MX31_PIN_SCK3, H2_PAD_CFG); /* USBH2_DATA5 */
imx_iomux_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */
imx_iomux_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */
tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x600);
tmp &= ~((3 << 21) | 1);
tmp |= (1 << 5) | (1 << 16) | (1 << 19) | (1 << 20);
writel(tmp, MX31_USB_OTG_BASE_ADDR + 0x600);
tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x584);
tmp &= ~(3 << 30);
tmp |= 2 << 30;
writel(tmp, MX31_USB_OTG_BASE_ADDR + 0x584);
mdelay(50);
ulpi_setup((void *)(MX31_USB_OTG_BASE_ADDR + 0x570), 1);
/* Set to Host mode */
tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x1a8);
writel(tmp | 0x3, MX31_USB_OTG_BASE_ADDR + 0x1a8);
}