Ejemplo n.º 1
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SLOT_INTERFACE_END

WRITE_LINE_MEMBER( vixen_state::fdc_intrq_w )
{
	m_fdint = state;
	update_interrupt();
}
Ejemplo n.º 2
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SLOT_INTERFACE_END

void vixen_state::fdc_intrq_w(bool state)
{
	m_fdint = state;
	update_interrupt();
}
Ejemplo n.º 3
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void vixen_state::machine_reset()
{
	membank("bank3")->set_entry(1);

	m_vsync = 0;
	m_cmd_d0 = 0;
	m_cmd_d1 = 0;
	update_interrupt();

	m_fdc->reset();
	m_io_i8155->reset();
	m_usart->reset();
	m_maincpu->set_state_int(Z80_PC, 0xf000);
}
Ejemplo n.º 4
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INPUT_PORTS_END



//**************************************************************************
//  DEVICE CONFIGURATION
//**************************************************************************

//-------------------------------------------------
//  mc146818_interface rtc_intf
//-------------------------------------------------

WRITE_LINE_MEMBER( hx20_state::rtc_irq_w )
{
	m_rtc_irq = state;

	update_interrupt();
}
Ejemplo n.º 5
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void vixen_state::machine_reset()
{
	address_space *program = m_maincpu->memory().space(AS_PROGRAM);

	program->install_read_bank(0x0000, 0xefff, 0xfff, 0, "bank1");
	program->install_write_bank(0x0000, 0xefff, 0xfff, 0, "bank2");

	memory_set_bank(m_machine, "bank1", 1);
	memory_set_bank(m_machine, "bank2", 1);
	memory_set_bank(m_machine, "bank3", 1);

	m_reset = 1;

	m_vsync = 0;
	m_cmd_d0 = 0;
	m_cmd_d1 = 0;
	update_interrupt();
}
Ejemplo n.º 6
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INPUT_PORTS_END



//**************************************************************************
//  VIDEO
//**************************************************************************

//-------------------------------------------------
//  TIMER_DEVICE_CALLBACK_MEMBER( vsync_tick )
//-------------------------------------------------

TIMER_DEVICE_CALLBACK_MEMBER(vixen_state::vsync_tick)
{
	if (m_cmd_d0)
	{
		m_vsync = 1;
		update_interrupt();
	}
}
Ejemplo n.º 7
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void dave_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
{
	switch (id)
	{
	case TIMER_1HZ:
		m_irq_status ^= IRQ_1HZ_DIVIDER;

		if (m_irq_status & IRQ_1HZ_DIVIDER)
			m_irq_status |= IRQ_1HZ_LATCH;
		break;

	case TIMER_50HZ:
		m_irq_status ^= IRQ_50HZ_DIVIDER;

		if (m_irq_status & IRQ_50HZ_DIVIDER)
			m_irq_status |= IRQ_50HZ_LATCH;
		break;
	}

	update_interrupt();
}
Ejemplo n.º 8
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void vixen_state::machine_reset()
{
	address_space &program = m_maincpu->space(AS_PROGRAM);

	program.install_read_bank(0x0000, 0xefff, 0xfff, 0, "bank1");
	program.install_write_bank(0x0000, 0xefff, 0xfff, 0, "bank2");

	membank("bank1")->set_entry(1);
	membank("bank2")->set_entry(1);
	membank("bank3")->set_entry(1);

	m_reset = 1;

	m_vsync = 0;
	m_cmd_d0 = 0;
	m_cmd_d1 = 0;
	update_interrupt();

	m_fdc->reset();
	m_io_i8155->reset();
	m_usart->reset();
}
Ejemplo n.º 9
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/* clear pending bit, if any ints are pending, then int will be triggered, otherwise it
will be cleared */
void ins8250_uart_device::clear_int(int flag)
{
	m_int_pending &= ~flag;
	update_interrupt();
}
Ejemplo n.º 10
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/* set pending bit and trigger int */
void ins8250_uart_device::trigger_int(int flag)
{
	m_int_pending |= flag;
	update_interrupt();
}