ssize_t show_time_in_state(struct device *dev, struct device_attribute *attr, char *buf)
{
struct kbase_device *kbdev;
ssize_t ret = 0;
int i;
kbdev = dev_get_drvdata(dev);
#ifdef CONFIG_MALI_T6XX_DVFS
update_time_in_state(mali_dvfs_status_current.step);
#endif
if (!kbdev)
return -ENODEV;
for (i = 0; i < MALI_DVFS_STEP; i++)
ret += snprintf(buf + ret, PAGE_SIZE - ret, "%d %llu\n", mali_dvfs_infotbl[i].clock, mali_dvfs_infotbl[i].time);
if (ret < PAGE_SIZE - 1)
ret += snprintf(buf + ret, PAGE_SIZE - ret, "\n");
else {
buf[PAGE_SIZE - 2] = '\n';
buf[PAGE_SIZE - 1] = '\0';
ret = PAGE_SIZE - 1;
}
return ret;
}
void kbase_platform_dvfs_set_level(kbase_device *kbdev, int level)
{
static int prev_level = -1;
if (level == prev_level)
return;
if (WARN_ON((level >= MALI_DVFS_STEP) || (level < 0)))
panic("invalid level");
#ifdef CONFIG_MALI_T6XX_FREQ_LOCK
if (mali_dvfs_status_current.upper_lock >= 0 && level > mali_dvfs_status_current.upper_lock)
level = mali_dvfs_status_current.upper_lock;
if (mali_dvfs_status_current.under_lock >= 0 && level < mali_dvfs_status_current.under_lock)
level = mali_dvfs_status_current.under_lock;
#endif
#ifdef CONFIG_MALI_T6XX_DVFS
mutex_lock(&mali_set_clock_lock);
#endif
kbase_platform_dvfs_set_clock(kbdev, mali_dvfs_infotbl[level].clock);
#if defined(CONFIG_MALI_T6XX_DEBUG_SYS) && defined(CONFIG_MALI_T6XX_DVFS)
update_time_in_state(prev_level);
#endif
prev_level = level;
#ifdef CONFIG_MALI_T6XX_DVFS
mutex_unlock(&mali_set_clock_lock);
#endif
}
void kbase_platform_dvfs_set_level(kbase_device *kbdev, int level)
{
static int prev_level = -1;
int f;
if (level == prev_level)
return;
if (WARN_ON((level >= MALI_DVFS_STEP)||(level < 0)))
panic("invalid level");
#ifdef CONFIG_MALI_T6XX_DVFS
mutex_lock(&mali_set_clock_lock);
#endif
f = mali_dvfs_infotbl[level].mem_freq;
if (level > prev_level) {
exynos5_bus_mif_update(mem_freq_req, f);
kbase_platform_dvfs_set_vol(mali_dvfs_infotbl[level].voltage);
kbase_platform_dvfs_set_clock(kbdev, mali_dvfs_infotbl[level].clock);
} else {
kbase_platform_dvfs_set_clock(kbdev, mali_dvfs_infotbl[level].clock);
kbase_platform_dvfs_set_vol(mali_dvfs_infotbl[level].voltage);
exynos5_bus_mif_update(mem_freq_req, f);
}
#if defined(CONFIG_MALI_T6XX_DEBUG_SYS) && defined(CONFIG_MALI_T6XX_DVFS)
update_time_in_state(prev_level);
#endif
prev_level = level;
#ifdef CONFIG_MALI_T6XX_DVFS
mutex_unlock(&mali_set_clock_lock);
#endif
}
void kbase_platform_dvfs_set_level(kbase_device *kbdev, int level)
{
static int prev_level = -1;
int mif_qos, int_qos, cpu_qos;
#ifdef MALI_DEBUG
printk(KERN_INFO "\n[mali_devfreq]dvfs level:%d\n", level);
#endif
if (level == prev_level)
return;
if (WARN_ON((level >= MALI_DVFS_STEP) || (level < 0)))
panic("invalid level");
#ifdef CONFIG_MALI_T6XX_DVFS
mutex_lock(&mali_set_clock_lock);
#endif
sec_debug_aux_log(SEC_DEBUG_AUXLOG_CPU_BUS_CLOCK_CHANGE,
"old:%7d new:%7d (G3D)",
mali_dvfs_infotbl[prev_level].clock*1000,
mali_dvfs_infotbl[level].clock*1000);
mif_qos = mali_dvfs_infotbl[level].mem_freq;
int_qos = mali_dvfs_infotbl[level].int_freq;
cpu_qos = mali_dvfs_infotbl[level].cpu_freq;
if (level > prev_level) {
#if defined(CONFIG_ARM_EXYNOS5420_BUS_DEVFREQ)
pm_qos_update_request(&exynos5_g3d_mif_qos, mif_qos);
pm_qos_update_request(&exynos5_g3d_int_qos, int_qos);
pm_qos_update_request(&exynos5_g3d_cpu_qos, cpu_qos);
#endif
kbase_platform_dvfs_set_vol(mali_dvfs_infotbl[level].voltage + gpu_voltage_margin);
kbase_platform_dvfs_set_clock(kbdev, mali_dvfs_infotbl[level].clock);
bts_change_g3d_state(mali_dvfs_infotbl[level].clock);
} else {
bts_change_g3d_state(mali_dvfs_infotbl[level].clock);
kbase_platform_dvfs_set_clock(kbdev, mali_dvfs_infotbl[level].clock);
kbase_platform_dvfs_set_vol(mali_dvfs_infotbl[level].voltage + gpu_voltage_margin);
#if defined(CONFIG_ARM_EXYNOS5420_BUS_DEVFREQ)
pm_qos_update_request(&exynos5_g3d_mif_qos, mif_qos);
pm_qos_update_request(&exynos5_g3d_int_qos, int_qos);
pm_qos_update_request(&exynos5_g3d_cpu_qos, cpu_qos);
#endif
}
#if defined(CONFIG_MALI_T6XX_DEBUG_SYS) && defined(CONFIG_MALI_T6XX_DVFS)
update_time_in_state(prev_level);
#endif
prev_level = level;
#ifdef CONFIG_MALI_T6XX_DVFS
mutex_unlock(&mali_set_clock_lock);
#endif
}
ssize_t show_time_in_state(struct device *dev, struct device_attribute *attr, char *buf)
{
ssize_t ret = 0;
int i;
update_time_in_state(maliDvfsStatus.currentStep);
for (i = 0; i < MALI_DVFS_STEPS; i++) {
ret += snprintf(buf + ret, PAGE_SIZE - ret, "%d %llu\n",
mali_dvfs[i].clock,
mali_dvfs_time[i]);
}
if (ret < PAGE_SIZE - 1) {
ret += snprintf(buf + ret, PAGE_SIZE - ret, "\n");
} else {
buf[PAGE_SIZE - 2] = '\n';
buf[PAGE_SIZE - 1] = '\0';
ret = PAGE_SIZE - 1;
}
return ret;
}
static int mali_devfreq_target(struct device *dev, unsigned long *freq, u32 flags)
{
unsigned int nextStatus = (unsigned int)*freq;
unsigned int curStatus = 0;
curStatus = maliDvfsStatus.currentStep;
MALI_DEBUG_PRINT(4, ("= curStatus %d, nextStatus %d, maliDvfsStatus.currentStep %d\n", curStatus, nextStatus, maliDvfsStatus.currentStep));
/*if next status is same with current status, don't change anything*/
if (curStatus != nextStatus) {
#if MALI_DVFS_CLK_DEBUG
unsigned int *pRegMaliClkDiv;
unsigned int *pRegMaliMpll;
#endif
if (nextStatus > curStatus) {
#ifdef CONFIG_MALI_DVFS
update_time_in_state(curStatus);
#endif
#ifdef CONFIG_REGULATOR
/*change the voltage*/
mali_regulator_set_voltage(get_match_volt(ID_G3D, mali_dvfs[nextStatus].clock * GPU_ASV_VOLT), get_match_volt(ID_G3D, mali_dvfs[nextStatus].clock * GPU_ASV_VOLT));
exynos_set_abb(ID_G3D, get_match_abb(ID_G3D, mali_dvfs[nextStatus].clock * GPU_ASV_VOLT));
#endif
/*change the clock*/
mali_clk_set_rate(mali_dvfs[nextStatus].clock, mali_dvfs[nextStatus].freq);
} else if (nextStatus < curStatus) {
#ifdef CONFIG_MALI_DVFS
update_time_in_state(curStatus);
#endif
/*change the clock*/
mali_clk_set_rate(mali_dvfs[nextStatus].clock, mali_dvfs[nextStatus].freq);
#ifdef CONFIG_REGULATOR
/*change the voltage*/
mali_regulator_set_voltage(get_match_volt(ID_G3D, mali_dvfs[nextStatus].clock * GPU_ASV_VOLT), get_match_volt(ID_G3D, mali_dvfs[nextStatus].clock * GPU_ASV_VOLT));
exynos_set_abb(ID_G3D, get_match_abb(ID_G3D, mali_dvfs[nextStatus].clock * GPU_ASV_VOLT));
#endif
} else
return 0;
#if defined(CONFIG_MALI400_PROFILING)
_mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE|
MALI_PROFILING_EVENT_CHANNEL_GPU|
MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
mali_gpu_clk, mali_gpu_vol/1000, 0, 0, 0);
#endif
mali_clk_put(MALI_FALSE);
#if MALI_DVFS_CLK_DEBUG
pRegMaliClkDiv = ioremap(0x1003c52c, 32);
pRegMaliMpll = ioremap(0x1003c22c, 32);
MALI_PRINT(("Mali MPLL reg:%d, CLK DIV: %d \n", *pRegMaliMpll, *pRegMaliClkDiv));
#endif
set_mali_dvfs_current_step(nextStatus);
/*for future use*/
maliDvfsStatus.pCurrentDvfs = &mali_dvfs[nextStatus];
#if CPUFREQ_LOCK_DURING_440
/* lock/unlock CPU freq by Mali */
if (mali_dvfs[nextStatus].clock >= 440)
cpufreq_lock_by_mali(400);
else
cpufreq_unlock_by_mali();
#endif
/*wait until clock and voltage is stablized*/
mali_platform_wating(MALI_DVFS_WATING); /*msec*/
}
return 0;
}
