static void _phy_lowpower_suspend(struct fsl_usb2_platform_data *pdata, bool enable)
{
u32 tmp;
void __iomem *phy_reg = MX6_IO_ADDRESS(USB_PHY1_BASE_ADDR);
pr_debug("host1, %s, enable is %d\n", __func__, enable);
if (enable) {
UH1_PORTSC1 |= PORTSC_PHCD;
pr_debug("%s, Poweroff UTMI \n", __func__);
tmp = (BM_USBPHY_PWD_TXPWDFS
| BM_USBPHY_PWD_TXPWDIBIAS
| BM_USBPHY_PWD_TXPWDV2I
| BM_USBPHY_PWD_RXPWDENV
| BM_USBPHY_PWD_RXPWD1PT1
| BM_USBPHY_PWD_RXPWDDIFF
| BM_USBPHY_PWD_RXPWDRX);
__raw_writel(tmp, phy_reg + HW_USBPHY_PWD_SET);
usbh1_internal_phy_clock_gate(false);
} else {
if (UH1_PORTSC1 & PORTSC_PHCD)
UH1_PORTSC1 &= ~PORTSC_PHCD;
/* Wait PHY clock stable */
mdelay(1);
usbh1_internal_phy_clock_gate(true);
udelay(2);
tmp = (BM_USBPHY_PWD_TXPWDFS
| BM_USBPHY_PWD_TXPWDIBIAS
| BM_USBPHY_PWD_TXPWDV2I
| BM_USBPHY_PWD_RXPWDENV
| BM_USBPHY_PWD_RXPWD1PT1
| BM_USBPHY_PWD_RXPWDDIFF
| BM_USBPHY_PWD_RXPWDRX);
__raw_writel(tmp, phy_reg + HW_USBPHY_PWD_CLR);
/*
* The PHY works at 32Khz clock when it is at low power mode,
* it needs 10 clocks from 32Khz to normal work state, so
* 500us is the safe value for PHY enters stable status
* according to IC engineer.
*/
udelay(500);
}
}
int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
struct usb_ehci *ehci;
enable_usboh3_clk(1);
mdelay(1);
/* Do board specific initialization */
board_ehci_hcd_init(CONFIG_MXC_USB_PORT);
#if CONFIG_MXC_USB_PORT == 1
/* USB Host 1 */
usbh1_power_config();
usbh1_oc_config();
usbh1_internal_phy_clock_gate(1);
usbh1_phy_enable();
#else
#error "MXC USB port not yet supported"
#endif
ehci = (struct usb_ehci *)(USBOH3_USB_BASE_ADDR +
(0x200 * CONFIG_MXC_USB_PORT));
*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
*hcor = (struct ehci_hcor *)((uint32_t)*hccr +
HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
setbits_le32(&ehci->usbmode, CM_HOST);
__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
setbits_le32(&ehci->portsc, USB_EN);
mdelay(10);
return 0;
}
static int fsl_usb_host_init_ext(struct platform_device *pdev)
{
static void __iomem *anatop_base_addr = MX6_IO_ADDRESS(ANATOP_BASE_ADDR);
int ret;
struct clk *usb_clk;
/* The PLL's power and output to usb for host 1
* is totally controlled by IC, so the Software only needs
* to enable them at initializtion. */
__raw_writel(BM_ANADIG_USB2_PLL_480_CTRL_BYPASS,
anatop_base_addr + HW_ANADIG_USB2_PLL_480_CTRL_CLR);
__raw_writel(BM_ANADIG_USB2_PLL_480_CTRL_ENABLE \
| BM_ANADIG_USB2_PLL_480_CTRL_POWER \
| BM_ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS, \
anatop_base_addr + HW_ANADIG_USB2_PLL_480_CTRL_SET);
usb_clk = clk_get(NULL, "usboh3_clk");
clk_enable(usb_clk);
usb_oh3_clk = usb_clk;
ret = fsl_usb_host_init(pdev);
if (ret) {
printk(KERN_ERR "host1 init fails......\n");
clk_disable(usb_oh3_clk);
clk_put(usb_oh3_clk);
return ret;
}
usbh1_internal_phy_clock_gate(true);
usb_phy_enable(pdev->dev.platform_data);
return 0;
}
static void _phy_lowpower_suspend(struct fsl_usb2_platform_data *pdata, bool enable)
{
u32 tmp;
void __iomem *phy_reg = MX6_IO_ADDRESS(USB_PHY1_BASE_ADDR);
pr_debug("host1, %s, enable is %d\n", __func__, enable);
if (enable) {
UH1_PORTSC1 |= PORTSC_PHCD;
pr_debug("%s, Poweroff UTMI \n", __func__);
tmp = (BM_USBPHY_PWD_TXPWDFS
| BM_USBPHY_PWD_TXPWDIBIAS
| BM_USBPHY_PWD_TXPWDV2I
| BM_USBPHY_PWD_RXPWDENV
| BM_USBPHY_PWD_RXPWD1PT1
| BM_USBPHY_PWD_RXPWDDIFF
| BM_USBPHY_PWD_RXPWDRX);
__raw_writel(tmp, phy_reg + HW_USBPHY_PWD_SET);
usbh1_internal_phy_clock_gate(false);
} else {
if (UH1_PORTSC1 & PORTSC_PHCD) {
UH1_PORTSC1 &= ~PORTSC_PHCD;
mdelay(1);
}
usbh1_internal_phy_clock_gate(true);
tmp = (BM_USBPHY_PWD_TXPWDFS
| BM_USBPHY_PWD_TXPWDIBIAS
| BM_USBPHY_PWD_TXPWDV2I
| BM_USBPHY_PWD_RXPWDENV
| BM_USBPHY_PWD_RXPWD1PT1
| BM_USBPHY_PWD_RXPWDDIFF
| BM_USBPHY_PWD_RXPWDRX);
__raw_writel(tmp, phy_reg + HW_USBPHY_PWD_CLR);
}
}
static int fsl_usb_host_init_ext(struct platform_device *pdev)
{
int ret;
struct clk *usb_clk;
usb_clk = clk_get(NULL, "usboh3_clk");
clk_enable(usb_clk);
usb_oh3_clk = usb_clk;
ret = fsl_usb_host_init(pdev);
if (ret) {
printk(KERN_ERR "host1 init fails......\n");
clk_disable(usb_oh3_clk);
clk_put(usb_oh3_clk);
return ret;
}
usbh1_internal_phy_clock_gate(true);
usb_phy_enable(pdev->dev.platform_data);
return 0;
}
static int fsl_usb_host_init_ext(struct platform_device *pdev)
{
int ret;
struct clk *usb_clk;
void __iomem *anatop_base_addr = MX6_IO_ADDRESS(ANATOP_BASE_ADDR);
usb_clk = clk_get(NULL, "usboh3_clk");
clk_enable(usb_clk);
usb_oh3_clk = usb_clk;
ret = fsl_usb_host_init(pdev);
if (ret) {
printk(KERN_ERR "host1 init fails......\n");
return ret;
}
usbh1_internal_phy_clock_gate(true);
usb_phy_enable(pdev->dev.platform_data);
usb_stop_mode_lock();
if (usb_stop_mode_refcount(true) == 1)
__raw_writel(BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG, anatop_base_addr + HW_ANADIG_ANA_MISC0_SET);
usb_stop_mode_unlock();
return 0;
}
