void usbhs_usbreq_set_val(struct usbhs_priv *priv, struct usb_ctrlrequest *req) { usbhs_write(priv, USBREQ, (req->bRequest << 8) | req->bRequestType); usbhs_write(priv, USBVAL, req->wValue); usbhs_write(priv, USBINDX, req->wIndex); usbhs_write(priv, USBLENG, req->wLength); usbhs_bset(priv, DCPCTR, SUREQ, SUREQ); }
static void usbhsf_fifo_unselect(struct usbhs_pipe *pipe, struct usbhs_fifo *fifo) { struct usbhs_priv *priv = usbhs_pipe_to_priv(pipe); usbhs_pipe_select_fifo(pipe, NULL); usbhs_write(priv, fifo->sel, 0); }
static irqreturn_t usbhs_interrupt(int irq, void *data) { struct usbhs_priv *priv = data; struct usbhs_irq_state irq_state; usbhs_status_get_each_irq(priv, &irq_state); usbhs_write(priv, INTSTS0, ~irq_state.intsts0 & INTSTS0_MAGIC); usbhs_write(priv, INTSTS1, ~irq_state.intsts1 & INTSTS1_MAGIC); usbhs_write(priv, BRDYSTS, 0); usbhs_write(priv, NRDYSTS, 0); usbhs_write(priv, BEMPSTS, 0); if (irq_state.intsts0 & VBINT) usbhs_mod_info_call(priv, irq_vbus, priv, &irq_state); if (irq_state.intsts0 & DVST) usbhs_mod_call(priv, irq_dev_state, priv, &irq_state); if (irq_state.intsts0 & CTRT) usbhs_mod_call(priv, irq_ctrl_stage, priv, &irq_state); if (irq_state.intsts0 & BEMP) usbhs_mod_call(priv, irq_empty, priv, &irq_state); if (irq_state.intsts0 & BRDY) usbhs_mod_call(priv, irq_ready, priv, &irq_state); if (irq_state.intsts1 & ATTCH) usbhs_mod_call(priv, irq_attch, priv, &irq_state); if (irq_state.intsts1 & DTCH) usbhs_mod_call(priv, irq_dtch, priv, &irq_state); if (irq_state.intsts1 & SIGN) usbhs_mod_call(priv, irq_sign, priv, &irq_state); if (irq_state.intsts1 & SACK) usbhs_mod_call(priv, irq_sack, priv, &irq_state); return IRQ_HANDLED; }
void usbhs_bset(struct usbhs_priv *priv, u32 reg, u16 mask, u16 data) { u16 val = usbhs_read(priv, reg); val &= ~mask; val |= data & mask; usbhs_write(priv, reg, val); }
static void usbhs_omap_tll_init(struct device *dev, u8 tll_channel_count) { struct usbhs_hcd_omap *omap = dev_get_drvdata(dev); struct usbhs_omap_platform_data *pdata = dev->platform_data; unsigned reg; int i; /* Program Common TLL register */ reg = usbhs_read(omap->tll_base, OMAP_TLL_SHARED_CONF); reg |= (OMAP_TLL_SHARED_CONF_FCLK_IS_ON | OMAP_TLL_SHARED_CONF_USB_DIVRATION); reg &= ~OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN; reg &= ~OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN; usbhs_write(omap->tll_base, OMAP_TLL_SHARED_CONF, reg); /* Enable channels now */ for (i = 0; i < tll_channel_count; i++) { reg = usbhs_read(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i)); if (is_ohci_port(pdata->port_mode[i])) { reg |= ohci_omap3_fslsmode(pdata->port_mode[i]) << OMAP_TLL_CHANNEL_CONF_FSLSMODE_SHIFT; reg |= OMAP_TLL_CHANNEL_CONF_CHANMODE_FSLS; } else if (pdata->port_mode[i] == OMAP_EHCI_PORT_MODE_TLL) { /* Disable AutoIdle, BitStuffing and use SDR Mode */ reg &= ~(OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE | OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF | OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE); reg |= (1 << (i + 1)); } else continue; reg |= OMAP_TLL_CHANNEL_CONF_CHANEN; usbhs_write(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i), reg); usbhs_writeb(omap->tll_base, OMAP_TLL_ULPI_SCRATCH_REGISTER(i), 0xbe); } }
static void usbhsf_fifo_clear(struct usbhs_pipe *pipe, struct usbhs_fifo *fifo) { struct usbhs_priv *priv = usbhs_pipe_to_priv(pipe); if (!usbhs_pipe_is_dcp(pipe)) usbhsf_fifo_barrier(priv, fifo); usbhs_write(priv, fifo->ctr, BCLR); }
/* * local functions */ static void usbhsc_bus_ctrl(struct usbhs_priv *priv, int enable) { int wait = usbhs_get_dparam(priv, buswait_bwait); u16 data = 0; if (enable) { /* set bus wait if platform have */ if (wait) usbhs_bset(priv, BUSWAIT, 0x000F, wait); } usbhs_write(priv, DVSTCTR, data); }
static int usbhsf_fifo_select(struct usbhs_pipe *pipe, struct usbhs_fifo *fifo, int write) { struct usbhs_priv *priv = usbhs_pipe_to_priv(pipe); struct device *dev = usbhs_priv_to_dev(priv); int timeout = 1024; u16 mask = ((1 << 5) | 0xF); /* mask of ISEL | CURPIPE */ u16 base = usbhs_pipe_number(pipe); /* CURPIPE */ if (usbhs_pipe_is_busy(pipe) || usbhsf_fifo_is_busy(fifo)) return -EBUSY; if (usbhs_pipe_is_dcp(pipe)) { base |= (1 == write) << 5; /* ISEL */ if (usbhs_mod_is_host(priv)) usbhs_dcp_dir_for_host(pipe, write); } /* "base" will be used below */ if (usbhs_get_dparam(priv, has_sudmac) && !usbhsf_is_cfifo(priv, fifo)) usbhs_write(priv, fifo->sel, base); else usbhs_write(priv, fifo->sel, base | MBW_32); /* check ISEL and CURPIPE value */ while (timeout--) { if (base == (mask & usbhs_read(priv, fifo->sel))) { usbhs_pipe_select_fifo(pipe, fifo); return 0; } udelay(10); } dev_err(dev, "fifo select error\n"); return -EIO; }
void usbhs_irq_callback_update(struct usbhs_priv *priv, struct usbhs_mod *mod) { u16 intenb0 = 0; u16 intenb1 = 0; struct usbhs_mod_info *info = usbhs_priv_to_modinfo(priv); usbhs_write(priv, INTENB0, 0); usbhs_write(priv, INTENB1, 0); usbhs_write(priv, BEMPENB, 0); usbhs_write(priv, BRDYENB, 0); if (info->irq_vbus) intenb0 |= VBSE; if (mod) { if (mod->irq_ctrl_stage) intenb0 |= CTRE; if (mod->irq_empty && mod->irq_bempsts) { usbhs_write(priv, BEMPENB, mod->irq_bempsts); intenb0 |= BEMPE; } if (mod->irq_ready && mod->irq_brdysts) { usbhs_write(priv, BRDYENB, mod->irq_brdysts); intenb0 |= BRDYE; } if (mod->irq_attch) intenb1 |= ATTCHE; if (mod->irq_dtch) intenb1 |= DTCHE; if (mod->irq_sign) intenb1 |= SIGNE; if (mod->irq_sack) intenb1 |= SACKE; } if (intenb0) usbhs_write(priv, INTENB0, intenb0); if (intenb1) usbhs_write(priv, INTENB1, intenb1); }
/* * pipe control functions */ static void usbhsp_pipe_select(struct usbhs_pipe *pipe) { struct usbhs_priv *priv = usbhs_pipe_to_priv(pipe); /* * On pipe, this is necessary before * accesses to below registers. * * PIPESEL : usbhsp_pipe_select * PIPECFG : usbhsp_pipe_cfg_xxx * PIPEBUF : usbhsp_pipe_buf_xxx * PIPEMAXP : usbhsp_pipe_maxp_xxx * PIPEPERI */ /* * if pipe is dcp, no pipe is selected. * it is no problem, because dcp have its register */ usbhs_write(priv, PIPESEL, 0xF & usbhs_pipe_number(pipe)); }
static int usbhsp_pipe_barrier(struct usbhs_pipe *pipe) { struct usbhs_priv *priv = usbhs_pipe_to_priv(pipe); int timeout = 1024; u16 val; /* * make sure.... * * Modify these bits when CSSTS = 0, PID = NAK, and no pipe number is * specified by the CURPIPE bits. * When changing the setting of this bit after changing * the PID bits for the selected pipe from BUF to NAK, * check that CSSTS = 0 and PBUSY = 0. */ /* * CURPIPE bit = 0 * * see also * "Operation" * - "Pipe Control" * - "Pipe Control Registers Switching Procedure" */ usbhs_write(priv, CFIFOSEL, 0); usbhs_pipe_disable(pipe); do { val = usbhsp_pipectrl_get(pipe); val &= CSSTS | PID_MASK; if (!val) return 0; udelay(10); } while (timeout--); return -EBUSY; }
/* * device configuration */ int usbhs_set_device_config(struct usbhs_priv *priv, int devnum, u16 upphub, u16 hubport, u16 speed) { struct device *dev = usbhs_priv_to_dev(priv); u16 usbspd = 0; u32 reg = DEVADD0 + (2 * devnum); if (devnum > 10) { dev_err(dev, "cannot set speed to unknown device %d\n", devnum); return -EIO; } if (upphub > 0xA) { dev_err(dev, "unsupported hub number %d\n", upphub); return -EIO; } switch (speed) { case USB_SPEED_LOW: usbspd = USBSPD_SPEED_LOW; break; case USB_SPEED_FULL: usbspd = USBSPD_SPEED_FULL; break; case USB_SPEED_HIGH: usbspd = USBSPD_SPEED_HIGH; break; default: dev_err(dev, "unsupported speed %d\n", speed); return -EIO; } usbhs_write(priv, reg, UPPHUB(upphub) | HUBPORT(hubport)| USBSPD(usbspd)); return 0; }
static void omap_usbhs_init(struct device *dev) { struct usbhs_hcd_omap *omap = dev_get_drvdata(dev); unsigned reg; dev_dbg(dev, "starting TI HSUSB Controller\n"); pm_runtime_get_sync(dev); reg = usbhs_read(omap->uhh_base, OMAP_UHH_HOSTCONFIG); /* setup ULPI bypass and burst configurations */ reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN); reg |= OMAP4_UHH_HOSTCONFIG_APP_START_CLK; reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN; switch (omap->usbhs_rev) { case OMAP_USBHS_REV1: reg = omap_usbhs_rev1_hostconfig(omap, reg); break; case OMAP_USBHS_REV2: reg = omap_usbhs_rev2_hostconfig(omap, reg); break; default: /* newer revisions */ reg = omap_usbhs_rev2_hostconfig(omap, reg); break; } usbhs_write(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg); dev_dbg(dev, "UHH setup done, uhh_hostconfig=%x\n", reg); pm_runtime_put_sync(dev); }
static void usbhsc_bus_init(struct usbhs_priv *priv) { usbhs_write(priv, DVSTCTR, 0); usbhs_vbus_ctrl(priv, 0); }
static int usbhs_enable(struct device *dev) { struct usbhs_hcd_omap *omap = dev_get_drvdata(dev); struct usbhs_omap_platform_data *pdata = &omap->platdata; unsigned long flags = 0; int ret = 0; unsigned reg; dev_dbg(dev, "starting TI HSUSB Controller\n"); if (!pdata) { dev_dbg(dev, "missing platform_data\n"); return -ENODEV; } spin_lock_irqsave(&omap->lock, flags); if (omap->count > 0) goto end_count; pm_runtime_get_sync(dev); if (pdata->ehci_data->phy_reset) { if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0])) { gpio_request(pdata->ehci_data->reset_gpio_port[0], "USB1 PHY reset"); gpio_direction_output (pdata->ehci_data->reset_gpio_port[0], 0); } if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1])) { gpio_request(pdata->ehci_data->reset_gpio_port[1], "USB2 PHY reset"); gpio_direction_output (pdata->ehci_data->reset_gpio_port[1], 0); } /* Hold the PHY in RESET for enough time till DIR is high */ udelay(10); } omap->usbhs_rev = usbhs_read(omap->uhh_base, OMAP_UHH_REVISION); dev_dbg(dev, "OMAP UHH_REVISION 0x%x\n", omap->usbhs_rev); reg = usbhs_read(omap->uhh_base, OMAP_UHH_HOSTCONFIG); /* setup ULPI bypass and burst configurations */ reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN); reg |= OMAP4_UHH_HOSTCONFIG_APP_START_CLK; reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN; if (is_omap_usbhs_rev1(omap)) { if (pdata->port_mode[0] == OMAP_USBHS_PORT_MODE_UNUSED) reg &= ~OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS; if (pdata->port_mode[1] == OMAP_USBHS_PORT_MODE_UNUSED) reg &= ~OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS; if (pdata->port_mode[2] == OMAP_USBHS_PORT_MODE_UNUSED) reg &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS; /* Bypass the TLL module for PHY mode operation */ if (cpu_is_omap3430() && (omap_rev() <= OMAP3430_REV_ES2_1)) { dev_dbg(dev, "OMAP3 ES version <= ES2.1\n"); if (is_ehci_phy_mode(pdata->port_mode[0]) || is_ehci_phy_mode(pdata->port_mode[1]) || is_ehci_phy_mode(pdata->port_mode[2])) reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_BYPASS; else reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS; } else { dev_dbg(dev, "OMAP3 ES version > ES2.1\n"); if (is_ehci_phy_mode(pdata->port_mode[0])) reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS; else reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS; if (is_ehci_phy_mode(pdata->port_mode[1])) reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS; else reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS; if (is_ehci_phy_mode(pdata->port_mode[2])) reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS; else reg |= OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS; } } else if (is_omap_usbhs_rev2(omap)) { /* Clear port mode fields for PHY mode*/ reg &= ~OMAP4_P1_MODE_CLEAR; reg &= ~OMAP4_P2_MODE_CLEAR; if (is_ehci_phy_mode(pdata->port_mode[0])) { ret = clk_set_parent(omap->utmi_p1_fck, omap->xclk60mhsp1_ck); if (ret != 0) { dev_err(dev, "xclk60mhsp1_ck set parent" "failed error:%d\n", ret); goto err_tll; } } else if (is_ehci_tll_mode(pdata->port_mode[0])) { ret = clk_set_parent(omap->utmi_p1_fck, omap->init_60m_fclk); if (ret != 0) { dev_err(dev, "init_60m_fclk set parent" "failed error:%d\n", ret); goto err_tll; } clk_enable(omap->usbhost_p1_fck); clk_enable(omap->usbtll_p1_fck); } if (is_ehci_phy_mode(pdata->port_mode[1])) { ret = clk_set_parent(omap->utmi_p2_fck, omap->xclk60mhsp2_ck); if (ret != 0) { dev_err(dev, "xclk60mhsp1_ck set parent" "failed error:%d\n", ret); goto err_tll; } } else if (is_ehci_tll_mode(pdata->port_mode[1])) { ret = clk_set_parent(omap->utmi_p2_fck, omap->init_60m_fclk); if (ret != 0) { dev_err(dev, "init_60m_fclk set parent" "failed error:%d\n", ret); goto err_tll; } clk_enable(omap->usbhost_p2_fck); clk_enable(omap->usbtll_p2_fck); } clk_enable(omap->utmi_p1_fck); clk_enable(omap->utmi_p2_fck); if (is_ehci_tll_mode(pdata->port_mode[0]) || (is_ohci_port(pdata->port_mode[0]))) reg |= OMAP4_P1_MODE_TLL; else if (is_ehci_hsic_mode(pdata->port_mode[0])) reg |= OMAP4_P1_MODE_HSIC; if (is_ehci_tll_mode(pdata->port_mode[1]) || (is_ohci_port(pdata->port_mode[1]))) reg |= OMAP4_P2_MODE_TLL; else if (is_ehci_hsic_mode(pdata->port_mode[1])) reg |= OMAP4_P2_MODE_HSIC; } usbhs_write(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg); dev_dbg(dev, "UHH setup done, uhh_hostconfig=%x\n", reg); if (is_ehci_tll_mode(pdata->port_mode[0]) || is_ehci_tll_mode(pdata->port_mode[1]) || is_ehci_tll_mode(pdata->port_mode[2]) || (is_ohci_port(pdata->port_mode[0])) || (is_ohci_port(pdata->port_mode[1])) || (is_ohci_port(pdata->port_mode[2]))) { /* Enable UTMI mode for required TLL channels */ if (is_omap_usbhs_rev2(omap)) usbhs_omap_tll_init(dev, OMAP_REV2_TLL_CHANNEL_COUNT); else usbhs_omap_tll_init(dev, OMAP_TLL_CHANNEL_COUNT); } if (pdata->ehci_data->phy_reset) { /* Hold the PHY in RESET for enough time till * PHY is settled and ready */ udelay(10); if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0])) gpio_set_value (pdata->ehci_data->reset_gpio_port[0], 1); if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1])) gpio_set_value (pdata->ehci_data->reset_gpio_port[1], 1); } end_count: omap->count++; spin_unlock_irqrestore(&omap->lock, flags); return 0; err_tll: pm_runtime_put_sync(dev); spin_unlock_irqrestore(&omap->lock, flags); if (pdata->ehci_data->phy_reset) { if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0])) gpio_free(pdata->ehci_data->reset_gpio_port[0]); if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1])) gpio_free(pdata->ehci_data->reset_gpio_port[1]); } return ret; }
void usbhs_sys_set_test_mode(struct usbhs_priv *priv, u16 mode) { usbhs_write(priv, TESTMODE, mode); }
/* * interrupt functions */ void usbhs_xxxsts_clear(struct usbhs_priv *priv, u16 sts_reg, u16 bit) { u16 pipe_mask = (u16)GENMASK(usbhs_get_dparam(priv, pipe_size), 0); usbhs_write(priv, sts_reg, ~(1 << bit) & pipe_mask); }
void usbhs_irq_callback_update(struct usbhs_priv *priv, struct usbhs_mod *mod) { u16 intenb0 = 0; u16 intenb1 = 0; struct usbhs_mod_info *info = usbhs_priv_to_modinfo(priv); /* * BEMPENB/BRDYENB are picky. * below method is required * * - clear INTSTS0 * - update BEMPENB/BRDYENB * - update INTSTS0 */ usbhs_write(priv, INTENB0, 0); usbhs_write(priv, INTENB1, 0); usbhs_write(priv, BEMPENB, 0); usbhs_write(priv, BRDYENB, 0); /* * see also * usbhs_interrupt */ /* * it don't enable DVSE (intenb0) here * but "mod->irq_dev_state" will be called. */ if (info->irq_vbus) intenb0 |= VBSE; if (mod) { /* * INTSTS0 */ if (mod->irq_ctrl_stage) intenb0 |= CTRE; if (mod->irq_empty && mod->irq_bempsts) { usbhs_write(priv, BEMPENB, mod->irq_bempsts); intenb0 |= BEMPE; } if (mod->irq_ready && mod->irq_brdysts) { usbhs_write(priv, BRDYENB, mod->irq_brdysts); intenb0 |= BRDYE; } /* * INTSTS1 */ if (mod->irq_attch) intenb1 |= ATTCHE; if (mod->irq_dtch) intenb1 |= DTCHE; if (mod->irq_sign) intenb1 |= SIGNE; if (mod->irq_sack) intenb1 |= SACKE; } if (intenb0) usbhs_write(priv, INTENB0, intenb0); if (intenb1) usbhs_write(priv, INTENB1, intenb1); }
/* * interrupt */ #define INTSTS0_MAGIC 0xF800 /* acknowledge magical interrupt sources */ #define INTSTS1_MAGIC 0xA870 /* acknowledge magical interrupt sources */ static irqreturn_t usbhs_interrupt(int irq, void *data) { struct usbhs_priv *priv = data; struct usbhs_irq_state irq_state; usbhs_status_get_each_irq(priv, &irq_state); /* * clear interrupt * * The hardware is _very_ picky to clear interrupt bit. * Especially INTSTS0_MAGIC, INTSTS1_MAGIC value. * * see * "Operation" * - "Control Transfer (DCP)" * - Function :: VALID bit should 0 */ usbhs_write(priv, INTSTS0, ~irq_state.intsts0 & INTSTS0_MAGIC); usbhs_write(priv, INTSTS1, ~irq_state.intsts1 & INTSTS1_MAGIC); usbhs_write(priv, BRDYSTS, 0); usbhs_write(priv, NRDYSTS, 0); usbhs_write(priv, BEMPSTS, 0); /* * call irq callback functions * see also * usbhs_irq_setting_update */ /* INTSTS0 */ if (irq_state.intsts0 & VBINT) usbhs_mod_info_call(priv, irq_vbus, priv, &irq_state); if (irq_state.intsts0 & DVST) usbhs_mod_call(priv, irq_dev_state, priv, &irq_state); if (irq_state.intsts0 & CTRT) usbhs_mod_call(priv, irq_ctrl_stage, priv, &irq_state); if (irq_state.intsts0 & BEMP) usbhs_mod_call(priv, irq_empty, priv, &irq_state); if (irq_state.intsts0 & BRDY) usbhs_mod_call(priv, irq_ready, priv, &irq_state); /* INTSTS1 */ if (irq_state.intsts1 & ATTCH) usbhs_mod_call(priv, irq_attch, priv, &irq_state); if (irq_state.intsts1 & DTCH) usbhs_mod_call(priv, irq_dtch, priv, &irq_state); if (irq_state.intsts1 & SIGN) usbhs_mod_call(priv, irq_sign, priv, &irq_state); if (irq_state.intsts1 & SACK) usbhs_mod_call(priv, irq_sack, priv, &irq_state); return IRQ_HANDLED; }
/* * interrupt */ #define INTSTS0_MAGIC 0xF800 /* acknowledge magical interrupt sources */ #define INTSTS1_MAGIC 0xA870 /* acknowledge magical interrupt sources */ static irqreturn_t usbhs_interrupt(int irq, void *data) { struct usbhs_priv *priv = data; struct usbhs_irq_state irq_state; if (usbhs_status_get_each_irq(priv, &irq_state) < 0) return IRQ_NONE; /* * clear interrupt * * The hardware is _very_ picky to clear interrupt bit. * Especially INTSTS0_MAGIC, INTSTS1_MAGIC value. * * see * "Operation" * - "Control Transfer (DCP)" * - Function :: VALID bit should 0 */ usbhs_write(priv, INTSTS0, ~irq_state.intsts0 & INTSTS0_MAGIC); if (usbhs_mod_is_host(priv)) usbhs_write(priv, INTSTS1, ~irq_state.intsts1 & INTSTS1_MAGIC); /* * The driver should not clear the xxxSTS after the line of * "call irq callback functions" because each "if" statement is * possible to call the callback function for avoiding any side effects. */ if (irq_state.intsts0 & BRDY) usbhs_write(priv, BRDYSTS, ~irq_state.brdysts); usbhs_write(priv, NRDYSTS, ~irq_state.nrdysts); if (irq_state.intsts0 & BEMP) usbhs_write(priv, BEMPSTS, ~irq_state.bempsts); /* * call irq callback functions * see also * usbhs_irq_setting_update */ /* INTSTS0 */ if (irq_state.intsts0 & VBINT) usbhs_mod_info_call(priv, irq_vbus, priv, &irq_state); if (irq_state.intsts0 & DVST) usbhs_mod_call(priv, irq_dev_state, priv, &irq_state); if (irq_state.intsts0 & CTRT) usbhs_mod_call(priv, irq_ctrl_stage, priv, &irq_state); if (irq_state.intsts0 & BEMP) usbhs_mod_call(priv, irq_empty, priv, &irq_state); if (irq_state.intsts0 & BRDY) usbhs_mod_call(priv, irq_ready, priv, &irq_state); if (usbhs_mod_is_host(priv)) { /* INTSTS1 */ if (irq_state.intsts1 & ATTCH) usbhs_mod_call(priv, irq_attch, priv, &irq_state); if (irq_state.intsts1 & DTCH) usbhs_mod_call(priv, irq_dtch, priv, &irq_state); if (irq_state.intsts1 & SIGN) usbhs_mod_call(priv, irq_sign, priv, &irq_state); if (irq_state.intsts1 & SACK) usbhs_mod_call(priv, irq_sack, priv, &irq_state); } return IRQ_HANDLED; }
static int usbhs_enable(struct device *dev) { struct usbhs_hcd_omap *omap = dev_get_drvdata(dev); struct usbhs_omap_platform_data *pdata = &omap->platdata; unsigned long flags = 0; int ret = 0; unsigned long timeout; unsigned reg; dev_dbg(dev, "starting TI HSUSB Controller\n"); if (!pdata) { dev_dbg(dev, "missing platform_data\n"); return -ENODEV; } spin_lock_irqsave(&omap->lock, flags); if (omap->count > 0) goto end_count; clk_enable(omap->usbhost_ick); clk_enable(omap->usbhost_hs_fck); clk_enable(omap->usbhost_fs_fck); clk_enable(omap->usbtll_fck); clk_enable(omap->usbtll_ick); if (pdata->ehci_data->phy_reset) { if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0])) { gpio_request(pdata->ehci_data->reset_gpio_port[0], "USB1 PHY reset"); gpio_direction_output (pdata->ehci_data->reset_gpio_port[0], 0); } if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1])) { gpio_request(pdata->ehci_data->reset_gpio_port[1], "USB2 PHY reset"); gpio_direction_output (pdata->ehci_data->reset_gpio_port[1], 0); } /* Hold the PHY in RESET for enough time till DIR is high */ udelay(10); } omap->usbhs_rev = usbhs_read(omap->uhh_base, OMAP_UHH_REVISION); dev_dbg(dev, "OMAP UHH_REVISION 0x%x\n", omap->usbhs_rev); /* perform TLL soft reset, and wait until reset is complete */ usbhs_write(omap->tll_base, OMAP_USBTLL_SYSCONFIG, OMAP_USBTLL_SYSCONFIG_SOFTRESET); /* Wait for TLL reset to complete */ timeout = jiffies + msecs_to_jiffies(1000); while (!(usbhs_read(omap->tll_base, OMAP_USBTLL_SYSSTATUS) & OMAP_USBTLL_SYSSTATUS_RESETDONE)) { cpu_relax(); if (time_after(jiffies, timeout)) { dev_dbg(dev, "operation timed out\n"); ret = -EINVAL; goto err_tll; } } dev_dbg(dev, "TLL RESET DONE\n"); /* (1<<3) = no idle mode only for initial debugging */ usbhs_write(omap->tll_base, OMAP_USBTLL_SYSCONFIG, OMAP_USBTLL_SYSCONFIG_ENAWAKEUP | OMAP_USBTLL_SYSCONFIG_SIDLEMODE | OMAP_USBTLL_SYSCONFIG_AUTOIDLE); /* Put UHH in NoIdle/NoStandby mode */ reg = usbhs_read(omap->uhh_base, OMAP_UHH_SYSCONFIG); if (is_omap_usbhs_rev1(omap)) { reg |= (OMAP_UHH_SYSCONFIG_ENAWAKEUP | OMAP_UHH_SYSCONFIG_SIDLEMODE | OMAP_UHH_SYSCONFIG_CACTIVITY | OMAP_UHH_SYSCONFIG_MIDLEMODE); reg &= ~OMAP_UHH_SYSCONFIG_AUTOIDLE; } else if (is_omap_usbhs_rev2(omap)) { reg &= ~OMAP4_UHH_SYSCONFIG_IDLEMODE_CLEAR; reg |= OMAP4_UHH_SYSCONFIG_NOIDLE; reg &= ~OMAP4_UHH_SYSCONFIG_STDBYMODE_CLEAR; reg |= OMAP4_UHH_SYSCONFIG_NOSTDBY; } usbhs_write(omap->uhh_base, OMAP_UHH_SYSCONFIG, reg); reg = usbhs_read(omap->uhh_base, OMAP_UHH_HOSTCONFIG); /* setup ULPI bypass and burst configurations */ reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN); reg |= OMAP4_UHH_HOSTCONFIG_APP_START_CLK; reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN; if (is_omap_usbhs_rev1(omap)) { if (pdata->port_mode[0] == OMAP_USBHS_PORT_MODE_UNUSED) reg &= ~OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS; if (pdata->port_mode[1] == OMAP_USBHS_PORT_MODE_UNUSED) reg &= ~OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS; if (pdata->port_mode[2] == OMAP_USBHS_PORT_MODE_UNUSED) reg &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS; /* Bypass the TLL module for PHY mode operation */ if (cpu_is_omap3430() && (omap_rev() <= OMAP3430_REV_ES2_1)) { dev_dbg(dev, "OMAP3 ES version <= ES2.1\n"); if (is_ehci_phy_mode(pdata->port_mode[0]) || is_ehci_phy_mode(pdata->port_mode[1]) || is_ehci_phy_mode(pdata->port_mode[2])) reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_BYPASS; else reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS; } else { dev_dbg(dev, "OMAP3 ES version > ES2.1\n"); if (is_ehci_phy_mode(pdata->port_mode[0])) reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS; else reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS; if (is_ehci_phy_mode(pdata->port_mode[1])) reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS; else reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS; if (is_ehci_phy_mode(pdata->port_mode[2])) reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS; else reg |= OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS; } } else if (is_omap_usbhs_rev2(omap)) { /* Clear port mode fields for PHY mode*/ reg &= ~OMAP4_P1_MODE_CLEAR; reg &= ~OMAP4_P2_MODE_CLEAR; if (is_ehci_phy_mode(pdata->port_mode[0])) { ret = clk_set_parent(omap->utmi_p1_fck, omap->xclk60mhsp1_ck); if (ret != 0) { dev_err(dev, "xclk60mhsp1_ck set parent" "failed error:%d\n", ret); goto err_tll; } } else if (is_ehci_tll_mode(pdata->port_mode[0])) { ret = clk_set_parent(omap->utmi_p1_fck, omap->init_60m_fclk); if (ret != 0) { dev_err(dev, "init_60m_fclk set parent" "failed error:%d\n", ret); goto err_tll; } clk_enable(omap->usbhost_p1_fck); clk_enable(omap->usbtll_p1_fck); } if (is_ehci_phy_mode(pdata->port_mode[1])) { ret = clk_set_parent(omap->utmi_p2_fck, omap->xclk60mhsp2_ck); if (ret != 0) { dev_err(dev, "xclk60mhsp1_ck set parent" "failed error:%d\n", ret); goto err_tll; } } else if (is_ehci_tll_mode(pdata->port_mode[1])) { ret = clk_set_parent(omap->utmi_p2_fck, omap->init_60m_fclk); if (ret != 0) { dev_err(dev, "init_60m_fclk set parent" "failed error:%d\n", ret); goto err_tll; } clk_enable(omap->usbhost_p2_fck); clk_enable(omap->usbtll_p2_fck); } clk_enable(omap->utmi_p1_fck); clk_enable(omap->utmi_p2_fck); if (is_ehci_tll_mode(pdata->port_mode[0]) || (is_ohci_port(pdata->port_mode[0]))) reg |= OMAP4_P1_MODE_TLL; else if (is_ehci_hsic_mode(pdata->port_mode[0])) reg |= OMAP4_P1_MODE_HSIC; if (is_ehci_tll_mode(pdata->port_mode[1]) || (is_ohci_port(pdata->port_mode[1]))) reg |= OMAP4_P2_MODE_TLL; else if (is_ehci_hsic_mode(pdata->port_mode[1])) reg |= OMAP4_P2_MODE_HSIC; } usbhs_write(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg); dev_dbg(dev, "UHH setup done, uhh_hostconfig=%x\n", reg); if (is_ehci_tll_mode(pdata->port_mode[0]) || is_ehci_tll_mode(pdata->port_mode[1]) || is_ehci_tll_mode(pdata->port_mode[2]) || (is_ohci_port(pdata->port_mode[0])) || (is_ohci_port(pdata->port_mode[1])) || (is_ohci_port(pdata->port_mode[2]))) { /* Enable UTMI mode for required TLL channels */ if (is_omap_usbhs_rev2(omap)) usbhs_omap_tll_init(dev, OMAP_REV2_TLL_CHANNEL_COUNT); else usbhs_omap_tll_init(dev, OMAP_TLL_CHANNEL_COUNT); } if (pdata->ehci_data->phy_reset) { /* Hold the PHY in RESET for enough time till * PHY is settled and ready */ udelay(10); if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0])) gpio_set_value (pdata->ehci_data->reset_gpio_port[0], 1); if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1])) gpio_set_value (pdata->ehci_data->reset_gpio_port[1], 1); } end_count: omap->count++; spin_unlock_irqrestore(&omap->lock, flags); return 0; err_tll: if (pdata->ehci_data->phy_reset) { if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0])) gpio_free(pdata->ehci_data->reset_gpio_port[0]); if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1])) gpio_free(pdata->ehci_data->reset_gpio_port[1]); } clk_disable(omap->usbtll_ick); clk_disable(omap->usbtll_fck); clk_disable(omap->usbhost_fs_fck); clk_disable(omap->usbhost_hs_fck); clk_disable(omap->usbhost_ick); spin_unlock_irqrestore(&omap->lock, flags); return ret; }
static void usbhs_disable(struct device *dev) { struct usbhs_hcd_omap *omap = dev_get_drvdata(dev); struct usbhs_omap_platform_data *pdata = &omap->platdata; unsigned long flags = 0; unsigned long timeout; dev_dbg(dev, "stopping TI HSUSB Controller\n"); spin_lock_irqsave(&omap->lock, flags); if (omap->count == 0) goto end_disble; omap->count--; if (omap->count != 0) goto end_disble; /* Reset OMAP modules for insmod/rmmod to work */ usbhs_write(omap->uhh_base, OMAP_UHH_SYSCONFIG, is_omap_usbhs_rev2(omap) ? OMAP4_UHH_SYSCONFIG_SOFTRESET : OMAP_UHH_SYSCONFIG_SOFTRESET); timeout = jiffies + msecs_to_jiffies(100); while (!(usbhs_read(omap->uhh_base, OMAP_UHH_SYSSTATUS) & (1 << 0))) { cpu_relax(); if (time_after(jiffies, timeout)) dev_dbg(dev, "operation timed out\n"); } while (!(usbhs_read(omap->uhh_base, OMAP_UHH_SYSSTATUS) & (1 << 1))) { cpu_relax(); if (time_after(jiffies, timeout)) dev_dbg(dev, "operation timed out\n"); } while (!(usbhs_read(omap->uhh_base, OMAP_UHH_SYSSTATUS) & (1 << 2))) { cpu_relax(); if (time_after(jiffies, timeout)) dev_dbg(dev, "operation timed out\n"); } usbhs_write(omap->tll_base, OMAP_USBTLL_SYSCONFIG, (1 << 1)); while (!(usbhs_read(omap->tll_base, OMAP_USBTLL_SYSSTATUS) & (1 << 0))) { cpu_relax(); if (time_after(jiffies, timeout)) dev_dbg(dev, "operation timed out\n"); } if (is_omap_usbhs_rev2(omap)) { if (is_ehci_tll_mode(pdata->port_mode[0])) clk_enable(omap->usbtll_p1_fck); if (is_ehci_tll_mode(pdata->port_mode[1])) clk_enable(omap->usbtll_p2_fck); clk_disable(omap->utmi_p2_fck); clk_disable(omap->utmi_p1_fck); } pm_runtime_put_sync(dev); /* The gpio_free migh sleep; so unlock the spinlock */ spin_unlock_irqrestore(&omap->lock, flags); if (pdata->ehci_data->phy_reset) { if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0])) gpio_free(pdata->ehci_data->reset_gpio_port[0]); if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1])) gpio_free(pdata->ehci_data->reset_gpio_port[1]); } return; end_disble: spin_unlock_irqrestore(&omap->lock, flags); }
static void omap_usbhs_init(struct device *dev) { struct usbhs_hcd_omap *omap = dev_get_drvdata(dev); struct usbhs_omap_platform_data *pdata = &omap->platdata; unsigned long flags; unsigned reg; dev_dbg(dev, "starting TI HSUSB Controller\n"); pm_runtime_get_sync(dev); spin_lock_irqsave(&omap->lock, flags); omap->usbhs_rev = usbhs_read(omap->uhh_base, OMAP_UHH_REVISION); dev_dbg(dev, "OMAP UHH_REVISION 0x%x\n", omap->usbhs_rev); reg = usbhs_read(omap->uhh_base, OMAP_UHH_HOSTCONFIG); /* setup ULPI bypass and burst configurations */ reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN); reg |= OMAP4_UHH_HOSTCONFIG_APP_START_CLK; reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN; if (is_omap_usbhs_rev1(omap)) { if (pdata->port_mode[0] == OMAP_USBHS_PORT_MODE_UNUSED) reg &= ~OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS; if (pdata->port_mode[1] == OMAP_USBHS_PORT_MODE_UNUSED) reg &= ~OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS; if (pdata->port_mode[2] == OMAP_USBHS_PORT_MODE_UNUSED) reg &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS; /* Bypass the TLL module for PHY mode operation */ if (cpu_is_omap3430() && (omap_rev() <= OMAP3430_REV_ES2_1)) { dev_dbg(dev, "OMAP3 ES version <= ES2.1\n"); if (is_ehci_phy_mode(pdata->port_mode[0]) || is_ehci_phy_mode(pdata->port_mode[1]) || is_ehci_phy_mode(pdata->port_mode[2])) reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_BYPASS; else reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS; } else { dev_dbg(dev, "OMAP3 ES version > ES2.1\n"); if (is_ehci_phy_mode(pdata->port_mode[0])) reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS; else reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS; if (is_ehci_phy_mode(pdata->port_mode[1])) reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS; else reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS; if (is_ehci_phy_mode(pdata->port_mode[2])) reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS; else reg |= OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS; } } else if (is_omap_usbhs_rev2(omap)) { /* Clear port mode fields for PHY mode*/ reg &= ~OMAP4_P1_MODE_CLEAR; reg &= ~OMAP4_P2_MODE_CLEAR; if (is_ehci_tll_mode(pdata->port_mode[0]) || (is_ohci_port(pdata->port_mode[0]))) reg |= OMAP4_P1_MODE_TLL; else if (is_ehci_hsic_mode(pdata->port_mode[0])) reg |= OMAP4_P1_MODE_HSIC; if (is_ehci_tll_mode(pdata->port_mode[1]) || (is_ohci_port(pdata->port_mode[1]))) reg |= OMAP4_P2_MODE_TLL; else if (is_ehci_hsic_mode(pdata->port_mode[1])) reg |= OMAP4_P2_MODE_HSIC; } usbhs_write(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg); dev_dbg(dev, "UHH setup done, uhh_hostconfig=%x\n", reg); if (is_ehci_tll_mode(pdata->port_mode[0]) || is_ehci_tll_mode(pdata->port_mode[1]) || is_ehci_tll_mode(pdata->port_mode[2]) || (is_ohci_port(pdata->port_mode[0])) || (is_ohci_port(pdata->port_mode[1])) || (is_ohci_port(pdata->port_mode[2]))) { /* Enable UTMI mode for required TLL channels */ if (is_omap_usbhs_rev2(omap)) usbhs_omap_tll_init(dev, OMAP_REV2_TLL_CHANNEL_COUNT); else usbhs_omap_tll_init(dev, OMAP_TLL_CHANNEL_COUNT); } spin_unlock_irqrestore(&omap->lock, flags); pm_runtime_put_sync(dev); }
static void omap_usbhs_init(struct device *dev) { struct usbhs_hcd_omap *omap = dev_get_drvdata(dev); struct usbhs_omap_platform_data *pdata = &omap->platdata; unsigned long flags = 0; unsigned reg; dev_dbg(dev, "starting TI HSUSB Controller\n"); pm_runtime_get_sync(dev); spin_lock_irqsave(&omap->lock, flags); if (pdata->ehci_data->phy_reset) { if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0])) { gpio_request(pdata->ehci_data->reset_gpio_port[0], "USB1 PHY reset"); gpio_direction_output (pdata->ehci_data->reset_gpio_port[0], 0); } if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1])) { gpio_request(pdata->ehci_data->reset_gpio_port[1], "USB2 PHY reset"); gpio_direction_output (pdata->ehci_data->reset_gpio_port[1], 0); } /* Hold the PHY in RESET for enough time till DIR is high */ udelay(10); } omap->usbhs_rev = usbhs_read(omap->uhh_base, OMAP_UHH_REVISION); dev_dbg(dev, "OMAP UHH_REVISION 0x%x\n", omap->usbhs_rev); /* * Really enable the port clocks * first call of pm_runtime_get_sync does not enable these * port clocks; because omap->usbhs_rev was not available * This omap->usbhs_rev is available now! */ usbhs_runtime_resume(dev); reg = usbhs_read(omap->uhh_base, OMAP_UHH_HOSTCONFIG); /* setup ULPI bypass and burst configurations */ reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN); /* Keep ENA_INCR_ALIGN = 0: Known to cause OCP delays */ reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN; if (is_omap_usbhs_rev1(omap)) { if (pdata->port_mode[0] == OMAP_USBHS_PORT_MODE_UNUSED) reg &= ~OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS; if (pdata->port_mode[1] == OMAP_USBHS_PORT_MODE_UNUSED) reg &= ~OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS; if (pdata->port_mode[2] == OMAP_USBHS_PORT_MODE_UNUSED) reg &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS; /* Bypass the TLL module for PHY mode operation */ if (cpu_is_omap3430() && (omap_rev() <= OMAP3430_REV_ES2_1)) { dev_dbg(dev, "OMAP3 ES version <= ES2.1\n"); if (is_ehci_phy_mode(pdata->port_mode[0]) || is_ehci_phy_mode(pdata->port_mode[1]) || is_ehci_phy_mode(pdata->port_mode[2])) reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_BYPASS; else reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS; } else { dev_dbg(dev, "OMAP3 ES version > ES2.1\n"); if (is_ehci_phy_mode(pdata->port_mode[0])) reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS; else reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS; if (is_ehci_phy_mode(pdata->port_mode[1])) reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS; else reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS; if (is_ehci_phy_mode(pdata->port_mode[2])) reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS; else reg |= OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS; } } else if (is_omap_usbhs_rev2(omap)) { /* Clear port mode fields for PHY mode*/ reg &= ~OMAP4_P1_MODE_CLEAR; reg &= ~OMAP4_P2_MODE_CLEAR; if (is_ehci_tll_mode(pdata->port_mode[0]) || (is_ohci_port(pdata->port_mode[0]))) reg |= OMAP4_P1_MODE_TLL; else if (is_ehci_hsic_mode(pdata->port_mode[0])) reg |= OMAP4_P1_MODE_HSIC; if (is_ehci_tll_mode(pdata->port_mode[1]) || (is_ohci_port(pdata->port_mode[1]))) reg |= OMAP4_P2_MODE_TLL; else if (is_ehci_hsic_mode(pdata->port_mode[1])) reg |= OMAP4_P2_MODE_HSIC; } usbhs_write(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg); dev_dbg(dev, "UHH setup done, uhh_hostconfig=%x\n", reg); if (is_ehci_tll_mode(pdata->port_mode[0]) || is_ehci_tll_mode(pdata->port_mode[1]) || is_ehci_tll_mode(pdata->port_mode[2]) || (is_ohci_port(pdata->port_mode[0])) || (is_ohci_port(pdata->port_mode[1])) || (is_ohci_port(pdata->port_mode[2]))) { /* Enable UTMI mode for required TLL channels */ if (is_omap_usbhs_rev2(omap)) usbhs_omap_tll_init(dev, OMAP_REV2_TLL_CHANNEL_COUNT); else usbhs_omap_tll_init(dev, OMAP_TLL_CHANNEL_COUNT); } if (pdata->ehci_data->phy_reset) { /* Hold the PHY in RESET for enough time till * PHY is settled and ready */ udelay(10); if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0])) gpio_set_value (pdata->ehci_data->reset_gpio_port[0], 1); if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1])) gpio_set_value (pdata->ehci_data->reset_gpio_port[1], 1); } spin_unlock_irqrestore(&omap->lock, flags); pm_runtime_put_sync(dev); }
static void omap_usbhs_init(struct device *dev) { struct usbhs_hcd_omap *omap = dev_get_drvdata(dev); struct usbhs_omap_platform_data *pdata = &omap->platdata; unsigned long flags; unsigned reg; dev_dbg(dev, "starting TI HSUSB Controller\n"); pm_runtime_get_sync(dev); if (pdata->ehci_data->phy_reset) { if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0])) gpio_request_one(pdata->ehci_data->reset_gpio_port[0], GPIOF_OUT_INIT_LOW, "USB1 PHY reset"); if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1])) gpio_request_one(pdata->ehci_data->reset_gpio_port[1], GPIOF_OUT_INIT_LOW, "USB2 PHY reset"); if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[2])) gpio_request_one(pdata->ehci_data->reset_gpio_port[2], GPIOF_OUT_INIT_LOW, "USB2 PHY reset"); /* Hold the PHY in RESET for enough time till DIR is high */ udelay(10); } spin_lock_irqsave(&omap->lock, flags); omap->usbhs_rev = usbhs_read(omap->uhh_base, OMAP_UHH_REVISION); dev_dbg(dev, "OMAP UHH_REVISION 0x%x\n", omap->usbhs_rev); reg = usbhs_read(omap->uhh_base, OMAP_UHH_HOSTCONFIG); /* setup ULPI bypass and burst configurations */ reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN); reg |= OMAP4_UHH_HOSTCONFIG_APP_START_CLK; reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN; if (is_omap_usbhs_rev1(omap)) { if (pdata->port_mode[0] == OMAP_USBHS_PORT_MODE_UNUSED) reg &= ~OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS; if (pdata->port_mode[1] == OMAP_USBHS_PORT_MODE_UNUSED) reg &= ~OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS; if (pdata->port_mode[2] == OMAP_USBHS_PORT_MODE_UNUSED) reg &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS; /* Bypass the TLL module for PHY mode operation */ if (cpu_is_omap3430() && (omap_rev() <= OMAP3430_REV_ES2_1)) { dev_dbg(dev, "OMAP3 ES version <= ES2.1\n"); if (is_ehci_phy_mode(pdata->port_mode[0]) || is_ehci_phy_mode(pdata->port_mode[1]) || is_ehci_phy_mode(pdata->port_mode[2])) reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_BYPASS; else reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS; } else { dev_dbg(dev, "OMAP3 ES version > ES2.1\n"); if (is_ehci_phy_mode(pdata->port_mode[0])) reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS; else reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS; if (is_ehci_phy_mode(pdata->port_mode[1])) reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS; else reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS; if (is_ehci_phy_mode(pdata->port_mode[2])) reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS; else reg |= OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS; } } else if (is_omap_usbhs_rev2(omap)) { /* Clear port mode fields for PHY mode*/ reg &= ~OMAP4_P1_MODE_CLEAR; reg &= ~OMAP4_P2_MODE_CLEAR; if (is_ehci_tll_mode(pdata->port_mode[0]) || (is_ohci_port(pdata->port_mode[0]))) reg |= OMAP4_P1_MODE_TLL; else if (is_ehci_hsic_mode(pdata->port_mode[0])) reg |= OMAP4_P1_MODE_HSIC; if (is_ehci_tll_mode(pdata->port_mode[1]) || (is_ohci_port(pdata->port_mode[1]))) reg |= OMAP4_P2_MODE_TLL; else if (is_ehci_hsic_mode(pdata->port_mode[1])) reg |= OMAP4_P2_MODE_HSIC; if (is_ehci_hsic_mode(pdata->port_mode[2])) reg |= OMAP5_P3_MODE_HSIC; } usbhs_write(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg); dev_dbg(dev, "UHH setup done, uhh_hostconfig=%x\n", reg); spin_unlock_irqrestore(&omap->lock, flags); if (pdata->ehci_data->phy_reset) { /* Hold the PHY in RESET for enough time till * PHY is settled and ready */ udelay(10); if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0])) gpio_set_value(pdata->ehci_data->reset_gpio_port[0], 1); if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1])) gpio_set_value(pdata->ehci_data->reset_gpio_port[1], 1); if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[2])) gpio_set_value(pdata->ehci_data->reset_gpio_port[2], 1); } pm_runtime_put_sync(dev); }