/**
* Draw vertex arrays, with optional indexing, optional instancing.
* All the other drawing functions are implemented in terms of this function.
* Basically, map the vertex buffers (and drawing surfaces), then hand off
* the drawing to the 'draw' module.
*/
static void
llvmpipe_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
{
struct llvmpipe_context *lp = llvmpipe_context(pipe);
struct draw_context *draw = lp->draw;
const void *mapped_indices = NULL;
unsigned i;
if (!llvmpipe_check_render_cond(lp))
return;
if (info->indirect) {
util_draw_indirect(pipe, info);
return;
}
if (lp->dirty)
llvmpipe_update_derived( lp );
/*
* Map vertex buffers
*/
for (i = 0; i < lp->num_vertex_buffers; i++) {
const void *buf = lp->vertex_buffer[i].is_user_buffer ?
lp->vertex_buffer[i].buffer.user : NULL;
size_t size = ~0;
if (!buf) {
if (!lp->vertex_buffer[i].buffer.resource) {
continue;
}
buf = llvmpipe_resource_data(lp->vertex_buffer[i].buffer.resource);
size = lp->vertex_buffer[i].buffer.resource->width0;
}
draw_set_mapped_vertex_buffer(draw, i, buf, size);
}
/* Map index buffer, if present */
if (info->index_size) {
unsigned available_space = ~0;
mapped_indices = info->has_user_indices ? info->index.user : NULL;
if (!mapped_indices) {
mapped_indices = llvmpipe_resource_data(info->index.resource);
available_space = info->index.resource->width0;
}
draw_set_indexes(draw,
(ubyte *) mapped_indices,
info->index_size, available_space);
}
for (i = 0; i < lp->num_so_targets; i++) {
void *buf = 0;
if (lp->so_targets[i]) {
buf = llvmpipe_resource(lp->so_targets[i]->target.buffer)->data;
lp->so_targets[i]->mapping = buf;
}
}
draw_set_mapped_so_targets(draw, lp->num_so_targets,
lp->so_targets);
llvmpipe_prepare_vertex_sampling(lp,
lp->num_sampler_views[PIPE_SHADER_VERTEX],
lp->sampler_views[PIPE_SHADER_VERTEX]);
llvmpipe_prepare_geometry_sampling(lp,
lp->num_sampler_views[PIPE_SHADER_GEOMETRY],
lp->sampler_views[PIPE_SHADER_GEOMETRY]);
if (lp->gs && lp->gs->no_tokens) {
/* we have an empty geometry shader with stream output, so
attach the stream output info to the current vertex shader */
if (lp->vs) {
draw_vs_attach_so(lp->vs, &lp->gs->stream_output);
}
}
draw_collect_pipeline_statistics(draw,
lp->active_statistics_queries > 0);
/* draw! */
draw_vbo(draw, info);
/*
* unmap vertex/index buffers
*/
for (i = 0; i < lp->num_vertex_buffers; i++) {
draw_set_mapped_vertex_buffer(draw, i, NULL, 0);
}
if (mapped_indices) {
draw_set_indexes(draw, NULL, 0, 0);
}
draw_set_mapped_so_targets(draw, 0, NULL);
if (lp->gs && lp->gs->no_tokens) {
/* we have attached stream output to the vs for rendering,
now lets reset it */
if (lp->vs) {
draw_vs_reset_so(lp->vs);
}
}
/*
* TODO: Flush only when a user vertex/index buffer is present
* (or even better, modify draw module to do this
* internally when this condition is seen?)
*/
draw_flush(draw);
}
/*
* Draw vertex arrays, with optional indexing, optional instancing.
*/
static void
swr_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
{
struct swr_context *ctx = swr_context(pipe);
if (!swr_check_render_cond(pipe))
return;
if (info->indirect) {
util_draw_indirect(pipe, info);
return;
}
/* Update derived state, pass draw info to update function */
if (ctx->dirty)
swr_update_derived(pipe, info);
swr_update_draw_context(ctx);
if (ctx->vs->pipe.stream_output.num_outputs) {
if (!ctx->vs->soFunc[info->mode]) {
STREAMOUT_COMPILE_STATE state = {0};
struct pipe_stream_output_info *so = &ctx->vs->pipe.stream_output;
state.numVertsPerPrim = u_vertices_per_prim(info->mode);
uint32_t offsets[MAX_SO_STREAMS] = {0};
uint32_t num = 0;
for (uint32_t i = 0; i < so->num_outputs; i++) {
assert(so->output[i].stream == 0); // @todo
uint32_t output_buffer = so->output[i].output_buffer;
if (so->output[i].dst_offset != offsets[output_buffer]) {
// hole - need to fill
state.stream.decl[num].bufferIndex = output_buffer;
state.stream.decl[num].hole = true;
state.stream.decl[num].componentMask =
(1 << (so->output[i].dst_offset - offsets[output_buffer]))
- 1;
num++;
offsets[output_buffer] = so->output[i].dst_offset;
}
state.stream.decl[num].bufferIndex = output_buffer;
state.stream.decl[num].attribSlot = so->output[i].register_index - 1;
state.stream.decl[num].componentMask =
((1 << so->output[i].num_components) - 1)
<< so->output[i].start_component;
state.stream.decl[num].hole = false;
num++;
offsets[output_buffer] += so->output[i].num_components;
}
state.stream.numDecls = num;
HANDLE hJitMgr = swr_screen(pipe->screen)->hJitMgr;
ctx->vs->soFunc[info->mode] = JitCompileStreamout(hJitMgr, state);
debug_printf("so shader %p\n", ctx->vs->soFunc[info->mode]);
assert(ctx->vs->soFunc[info->mode] && "Error: SoShader = NULL");
}
SwrSetSoFunc(ctx->swrContext, ctx->vs->soFunc[info->mode], 0);
}
struct swr_vertex_element_state *velems = ctx->velems;
if (!velems->fsFunc
|| (velems->fsState.cutIndex != info->restart_index)
|| (velems->fsState.bEnableCutIndex != info->primitive_restart)) {
velems->fsState.cutIndex = info->restart_index;
velems->fsState.bEnableCutIndex = info->primitive_restart;
/* Create Fetch Shader */
HANDLE hJitMgr = swr_screen(ctx->pipe.screen)->hJitMgr;
velems->fsFunc = JitCompileFetch(hJitMgr, velems->fsState);
debug_printf("fetch shader %p\n", velems->fsFunc);
assert(velems->fsFunc && "Error: FetchShader = NULL");
}
SwrSetFetchFunc(ctx->swrContext, velems->fsFunc);
/* Set up frontend state
* XXX setup provokingVertex & topologyProvokingVertex */
SWR_FRONTEND_STATE feState = {0};
if (ctx->rasterizer->flatshade_first) {
feState.provokingVertex = {1, 0, 0};
} else {
feState.provokingVertex = {2, 1, 2};
}
switch (info->mode) {
case PIPE_PRIM_TRIANGLE_FAN:
feState.topologyProvokingVertex = feState.provokingVertex.triFan;
break;
case PIPE_PRIM_TRIANGLE_STRIP:
case PIPE_PRIM_TRIANGLES:
feState.topologyProvokingVertex = feState.provokingVertex.triStripList;
break;
case PIPE_PRIM_QUAD_STRIP:
case PIPE_PRIM_QUADS:
if (ctx->rasterizer->flatshade_first)
feState.topologyProvokingVertex = 0;
else
feState.topologyProvokingVertex = 3;
break;
case PIPE_PRIM_LINES:
case PIPE_PRIM_LINE_LOOP:
case PIPE_PRIM_LINE_STRIP:
feState.topologyProvokingVertex = feState.provokingVertex.lineStripList;
break;
default:
feState.topologyProvokingVertex = 0;
}
feState.bEnableCutIndex = info->primitive_restart;
SwrSetFrontendState(ctx->swrContext, &feState);
if (info->indexed)
SwrDrawIndexedInstanced(ctx->swrContext,
swr_convert_prim_topology(info->mode),
info->count,
info->instance_count,
info->start,
info->index_bias,
info->start_instance);
else
SwrDrawInstanced(ctx->swrContext,
swr_convert_prim_topology(info->mode),
info->count,
info->instance_count,
info->start,
info->start_instance);
}
/*
* Draw vertex arrays, with optional indexing, optional instancing.
*/
static void
swr_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
{
struct swr_context *ctx = swr_context(pipe);
if (!info->count_from_stream_output && !info->indirect &&
!info->primitive_restart &&
!u_trim_pipe_prim(info->mode, (unsigned*)&info->count))
return;
if (!swr_check_render_cond(pipe))
return;
if (info->indirect) {
util_draw_indirect(pipe, info);
return;
}
/* If indexed draw, force vertex validation since index buffer comes
* from draw info. */
if (info->index_size)
ctx->dirty |= SWR_NEW_VERTEX;
/* Update derived state, pass draw info to update function. */
swr_update_derived(pipe, info);
swr_update_draw_context(ctx);
if (ctx->vs->pipe.stream_output.num_outputs) {
if (!ctx->vs->soFunc[info->mode]) {
STREAMOUT_COMPILE_STATE state = {0};
struct pipe_stream_output_info *so = &ctx->vs->pipe.stream_output;
state.numVertsPerPrim = u_vertices_per_prim(info->mode);
uint32_t offsets[MAX_SO_STREAMS] = {0};
uint32_t num = 0;
for (uint32_t i = 0; i < so->num_outputs; i++) {
assert(so->output[i].stream == 0); // @todo
uint32_t output_buffer = so->output[i].output_buffer;
if (so->output[i].dst_offset != offsets[output_buffer]) {
// hole - need to fill
state.stream.decl[num].bufferIndex = output_buffer;
state.stream.decl[num].hole = true;
state.stream.decl[num].componentMask =
(1 << (so->output[i].dst_offset - offsets[output_buffer]))
- 1;
num++;
offsets[output_buffer] = so->output[i].dst_offset;
}
unsigned attrib_slot = so->output[i].register_index;
attrib_slot = swr_so_adjust_attrib(attrib_slot, ctx->vs);
state.stream.decl[num].bufferIndex = output_buffer;
state.stream.decl[num].attribSlot = attrib_slot;
state.stream.decl[num].componentMask =
((1 << so->output[i].num_components) - 1)
<< so->output[i].start_component;
state.stream.decl[num].hole = false;
num++;
offsets[output_buffer] += so->output[i].num_components;
}
state.stream.numDecls = num;
HANDLE hJitMgr = swr_screen(pipe->screen)->hJitMgr;
ctx->vs->soFunc[info->mode] = JitCompileStreamout(hJitMgr, state);
debug_printf("so shader %p\n", ctx->vs->soFunc[info->mode]);
assert(ctx->vs->soFunc[info->mode] && "Error: SoShader = NULL");
}
ctx->api.pfnSwrSetSoFunc(ctx->swrContext, ctx->vs->soFunc[info->mode], 0);
}
struct swr_vertex_element_state *velems = ctx->velems;
if (info->primitive_restart)
velems->fsState.cutIndex = info->restart_index;
else
velems->fsState.cutIndex = 0;
velems->fsState.bEnableCutIndex = info->primitive_restart;
velems->fsState.bPartialVertexBuffer = (info->min_index > 0);
swr_jit_fetch_key key;
swr_generate_fetch_key(key, velems);
auto search = velems->map.find(key);
if (search != velems->map.end()) {
velems->fsFunc = search->second;
} else {
HANDLE hJitMgr = swr_screen(ctx->pipe.screen)->hJitMgr;
velems->fsFunc = JitCompileFetch(hJitMgr, velems->fsState);
debug_printf("fetch shader %p\n", velems->fsFunc);
assert(velems->fsFunc && "Error: FetchShader = NULL");
velems->map.insert(std::make_pair(key, velems->fsFunc));
}
ctx->api.pfnSwrSetFetchFunc(ctx->swrContext, velems->fsFunc);
/* Set up frontend state
* XXX setup provokingVertex & topologyProvokingVertex */
SWR_FRONTEND_STATE feState = {0};
// feState.vsVertexSize seeds the PA size that is used as an interface
// between all the shader stages, so it has to be large enough to
// incorporate all interfaces between stages
// max of gs and vs num_outputs
feState.vsVertexSize = ctx->vs->info.base.num_outputs;
if (ctx->gs &&
ctx->gs->info.base.num_outputs > feState.vsVertexSize) {
feState.vsVertexSize = ctx->gs->info.base.num_outputs;
}
if (ctx->vs->info.base.num_outputs) {
// gs does not adjust for position in SGV slot at input from vs
if (!ctx->gs)
feState.vsVertexSize--;
}
// other (non-SGV) slots start at VERTEX_ATTRIB_START_SLOT
feState.vsVertexSize += VERTEX_ATTRIB_START_SLOT;
// The PA in the clipper does not handle BE vertex sizes
// different from FE. Increase vertexsize only for the cases that needed it
// primid needs a slot
if (ctx->fs->info.base.uses_primid)
feState.vsVertexSize++;
// sprite coord enable
if (ctx->rasterizer->sprite_coord_enable)
feState.vsVertexSize++;
if (ctx->rasterizer->flatshade_first) {
feState.provokingVertex = {1, 0, 0};
} else {
feState.provokingVertex = {2, 1, 2};
}
enum pipe_prim_type topology;
if (ctx->gs)
topology = (pipe_prim_type)ctx->gs->info.base.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
else
topology = info->mode;
switch (topology) {
case PIPE_PRIM_TRIANGLE_FAN:
feState.topologyProvokingVertex = feState.provokingVertex.triFan;
break;
case PIPE_PRIM_TRIANGLE_STRIP:
case PIPE_PRIM_TRIANGLES:
feState.topologyProvokingVertex = feState.provokingVertex.triStripList;
break;
case PIPE_PRIM_QUAD_STRIP:
case PIPE_PRIM_QUADS:
if (ctx->rasterizer->flatshade_first)
feState.topologyProvokingVertex = 0;
else
feState.topologyProvokingVertex = 3;
break;
case PIPE_PRIM_LINES:
case PIPE_PRIM_LINE_LOOP:
case PIPE_PRIM_LINE_STRIP:
feState.topologyProvokingVertex = feState.provokingVertex.lineStripList;
break;
default:
feState.topologyProvokingVertex = 0;
}
feState.bEnableCutIndex = info->primitive_restart;
ctx->api.pfnSwrSetFrontendState(ctx->swrContext, &feState);
if (info->index_size)
ctx->api.pfnSwrDrawIndexedInstanced(ctx->swrContext,
swr_convert_prim_topology(info->mode),
info->count,
info->instance_count,
info->start,
info->index_bias,
info->start_instance);
else
ctx->api.pfnSwrDrawInstanced(ctx->swrContext,
swr_convert_prim_topology(info->mode),
info->count,
info->instance_count,
info->start,
info->start_instance);
/* On large client-buffer draw, we used client buffer directly, without
* copy. Block until draw is finished.
* VMD is an example application that benefits from this. */
if (ctx->dirty & SWR_LARGE_CLIENT_DRAW) {
struct swr_screen *screen = swr_screen(pipe->screen);
swr_fence_submit(ctx, screen->flush_fence);
swr_fence_finish(pipe->screen, NULL, screen->flush_fence, 0);
}
}
