int cleanup_before_linux(void)
{
/*
* this function is called just before we call linux
* it prepares the processor for linux
*
* we turn off caches etc ...
*/
#ifndef CONFIG_SPL_BUILD
disable_interrupts();
#ifdef CONFIG_LCD
{
/* switch off LCD panel */
lcd_panel_disable();
/* disable LCD controller */
lcd_disable();
}
#endif /* CONFIG_LCD */
#endif /* CONFIG_SPL_BUILD */
/*
* Turn off I-cache and invalidate it
*/
icache_disable();
invalidate_icache_all();
/*
* turn off D-cache
* dcache_disable() in turn flushes the d-cache and disables MMU
*/
dcache_disable();
v7_outer_cache_disable();
/*
* After D-cache is flushed and before it is disabled there may
* be some new valid entries brought into the cache. We are sure
* that these lines are not dirty and will not affect our execution.
* (because unwinding the call-stack and setting a bit in CP15 SCTRL
* is all we did during this. We have not pushed anything on to the
* stack. Neither have we affected any static data)
* So just invalidate the entire d-cache again to avoid coherency
* problems for kernel
*/
invalidate_dcache_all();
/*
* Some CPU need more cache attention before starting the kernel.
*/
cpu_cache_initialization();
return 0;
}
int cleanup_before_linux(void)
{
#ifdef CONFIG_BOOTSTAGE_REPORT
bootstage_report();
#endif
#ifdef CONFIG_BOOTSTAGE_STASH
bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH,
CONFIG_BOOTSTAGE_STASH_SIZE);
#endif
/*
* this function is called just before we call linux
* it prepares the processor for linux
*
* we turn off caches etc ...
*/
disable_interrupts();
#ifdef CONFIG_EXYNOS_LCD
exynos_fimd_disable();
#endif
/*
* Turn off I-cache and invalidate it
*/
icache_disable();
invalidate_icache_all();
/*
* turn off D-cache
* dcache_disable() in turn flushes the d-cache and disables MMU
*/
dcache_disable();
v7_outer_cache_disable();
/*
* After D-cache is flushed and before it is disabled there may
* be some new valid entries brought into the cache. We are sure
* that these lines are not dirty and will not affect our execution.
* (because unwinding the call-stack and setting a bit in CP15 SCTRL
* is all we did during this. We have not pushed anything on to the
* stack. Neither have we affected any static data)
* So just invalidate the entire d-cache again to avoid coherency
* problems for kernel
*/
invalidate_dcache_all();
return 0;
}
void reset_cpu(ulong ignored)
{
disable_interrupts();
FW_NandDeInit();
#ifndef CONFIG_SYS_L2CACHE_OFF
v7_outer_cache_disable();
#endif
#ifndef CONFIG_SYS_DCACHE_OFF
flush_dcache_all();
#endif
#ifndef CONFIG_SYS_ICACHE_OFF
invalidate_icache_all();
#endif
#ifndef CONFIG_SYS_DCACHE_OFF
dcache_disable();
#endif
#ifndef CONFIG_SYS_ICACHE_OFF
icache_disable();
#endif
#if defined(CONFIG_RKCHIP_RK3288)
/* pll enter slow mode */
writel(PLL_MODE_SLOW(APLL_ID) | PLL_MODE_SLOW(GPLL_ID) | PLL_MODE_SLOW(CPLL_ID) | PLL_MODE_SLOW(NPLL_ID), RKIO_GRF_PHYS + CRU_MODE_CON);
/* soft reset */
writel(0xeca8, RKIO_CRU_PHYS + CRU_GLB_SRST_SND);
#elif defined(CONFIG_RKCHIP_RK3036)
/* pll enter slow mode */
writel(PLL_MODE_SLOW(APLL_ID) | PLL_MODE_SLOW(GPLL_ID), RKIO_GRF_PHYS + CRU_MODE_CON);
/* soft reset */
writel(0xeca8, RKIO_CRU_PHYS + CRU_GLB_SRST_SND);
#elif defined(CONFIG_RKCHIP_RK3126) || defined(CONFIG_RKCHIP_RK3128)
/* pll enter slow mode */
writel(PLL_MODE_SLOW(APLL_ID) | PLL_MODE_SLOW(CPLL_ID) | PLL_MODE_SLOW(GPLL_ID), RKIO_GRF_PHYS + CRU_MODE_CON);
/* soft reset */
writel(0xeca8, RKIO_CRU_PHYS + CRU_GLB_SRST_SND);
#else
#error "PLS config platform for reset.c!"
#endif /* CONFIG_RKPLATFORM */
}
void reset_cpu(ulong ignored)
{
disable_interrupts();
FW_NandDeInit();
#ifndef CONFIG_SYS_L2CACHE_OFF
v7_outer_cache_disable();
#endif
#ifndef CONFIG_SYS_DCACHE_OFF
flush_dcache_all();
#endif
#ifndef CONFIG_SYS_ICACHE_OFF
invalidate_icache_all();
#endif
#ifndef CONFIG_SYS_DCACHE_OFF
dcache_disable();
#endif
#ifndef CONFIG_SYS_ICACHE_OFF
icache_disable();
#endif
#if (CONFIG_RKCHIPTYPE == CONFIG_RK3288)
/* disable remap */
/* rk3288 address remap control bit: SGRF soc con0 bit 11 */
writel(1 << (11 + 16), RKIO_SECURE_GRF_PHYS + SGRF_SOC_CON0);
/* pll enter slow mode */
writel(PLL_MODE_SLOW(APLL_ID) | PLL_MODE_SLOW(GPLL_ID) | PLL_MODE_SLOW(CPLL_ID) | PLL_MODE_SLOW(NPLL_ID), RKIO_GRF_PHYS + CRU_MODE_CON);
/* soft reset */
writel(0xeca8, RKIO_CRU_PHYS + CRU_GLB_SRST_SND);
#else
#error "PLS config platform for reset.c!"
#endif /* CONFIG_RKPLATFORM */
}
void reset_cpu(ulong ignored)
{
disable_interrupts();
FW_NandDeInit();
#ifndef CONFIG_SYS_L2CACHE_OFF
v7_outer_cache_disable();
#endif
#ifndef CONFIG_SYS_DCACHE_OFF
flush_dcache_all();
#endif
#ifndef CONFIG_SYS_ICACHE_OFF
invalidate_icache_all();
#endif
#ifndef CONFIG_SYS_DCACHE_OFF
dcache_disable();
#endif
#ifndef CONFIG_SYS_ICACHE_OFF
icache_disable();
#endif
#if defined(CONFIG_RKCHIP_RK3368)
/* pll enter slow mode */
cru_writel(((0x00 << 8) && (0x03 << 24)), PLL_CONS(APLLB_ID, 3));
cru_writel(((0x00 << 8) && (0x03 << 24)), PLL_CONS(APLLL_ID, 3));
cru_writel(((0x00 << 8) && (0x03 << 24)), PLL_CONS(GPLL_ID, 3));
cru_writel(((0x00 << 8) && (0x03 << 24)), PLL_CONS(CPLL_ID, 3));
cru_writel(((0x00 << 8) && (0x03 << 24)), PLL_CONS(NPLL_ID, 3));
/* soft reset */
writel(0xeca8, RKIO_CRU_PHYS + CRU_GLB_SRST_SND);
#else
#error "PLS config platform for reset.c!"
#endif /* CONFIG_RKPLATFORM */
}
