static int reserve_video(void)
{
#ifdef CONFIG_DM_VIDEO
ulong addr;
int ret;
addr = gd->relocaddr;
ret = video_reserve(&addr);
if (ret)
return ret;
gd->relocaddr = addr;
#elif defined(CONFIG_LCD)
# ifdef CONFIG_FB_ADDR
gd->fb_base = CONFIG_FB_ADDR;
# else
/* reserve memory for LCD display (always full pages) */
gd->relocaddr = lcd_setmem(gd->relocaddr);
gd->fb_base = gd->relocaddr;
# endif /* CONFIG_FB_ADDR */
#elif defined(CONFIG_VIDEO) && \
(!defined(CONFIG_PPC)) && \
!defined(CONFIG_ARM) && !defined(CONFIG_X86) && \
!defined(CONFIG_M68K)
/* reserve memory for video display (always full pages) */
gd->relocaddr = video_setmem(gd->relocaddr);
gd->fb_base = gd->relocaddr;
#endif
return 0;
}
static int reserve_video(void)
{
/* reserve memory for video display (always full pages) */
gd->relocaddr = video_setmem(gd->relocaddr);
gd->fb_base = gd->relocaddr;
return 0;
}
void board_init_f(ulong bootflag)
{
bd_t *bd;
ulong len, addr, addr_sp;
ulong *s;
gd_t *id;
init_fnc_t **init_fnc_ptr;
#ifdef CONFIG_PRAM
ulong reg;
#endif
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
/* compiler optimization barrier needed for GCC >= 3.4 */
__asm__ __volatile__("":::"memory");
#if !defined(CONFIG_CPM2) && !defined(CONFIG_MPC512X) && \
!defined(CONFIG_MPC83xx) && !defined(CONFIG_MPC85xx) && \
!defined(CONFIG_MPC86xx)
/* Clear initial global data */
memset((void *) gd, 0, sizeof(gd_t));
#endif
gd->flags = bootflag;
for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr)
if ((*init_fnc_ptr) () != 0)
hang();
#ifdef CONFIG_POST
post_bootmode_init();
post_run(NULL, POST_ROM | post_bootmode_get(NULL));
#endif
WATCHDOG_RESET();
/*
* Now that we have DRAM mapped and working, we can
* relocate the code and continue running from DRAM.
*
* Reserve memory at end of RAM for (top down in that order):
* - area that won't get touched by U-Boot and Linux (optional)
* - kernel log buffer
* - protected RAM
* - LCD framebuffer
* - monitor code
* - board info struct
*/
len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
/*
* Subtract specified amount of memory to hide so that it won't
* get "touched" at all by U-Boot. By fixing up gd->ram_size
* the Linux kernel should now get passed the now "corrected"
* memory size and won't touch it either. This should work
* for arch/ppc and arch/powerpc. Only Linux board ports in
* arch/powerpc with bootwrapper support, that recalculate the
* memory size from the SDRAM controller setup will have to
* get fixed.
*/
gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;
addr = CONFIG_SYS_SDRAM_BASE + get_effective_memsize();
#if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
/*
* We need to make sure the location we intend to put secondary core
* boot code is reserved and not used by any part of u-boot
*/
if (addr > determine_mp_bootpg(NULL)) {
addr = determine_mp_bootpg(NULL);
debug("Reserving MP boot page to %08lx\n", addr);
}
#endif
#ifdef CONFIG_LOGBUFFER
#ifndef CONFIG_ALT_LB_ADDR
/* reserve kernel log buffer */
addr -= (LOGBUFF_RESERVE);
debug("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN,
addr);
#endif
#endif
#ifdef CONFIG_PRAM
/*
* reserve protected RAM
*/
reg = getenv_ulong("pram", 10, CONFIG_PRAM);
addr -= (reg << 10); /* size is in kB */
debug("Reserving %ldk for protected RAM at %08lx\n", reg, addr);
#endif /* CONFIG_PRAM */
/* round down to next 4 kB limit */
addr &= ~(4096 - 1);
debug("Top of RAM usable for U-Boot at: %08lx\n", addr);
#ifdef CONFIG_LCD
#ifdef CONFIG_FB_ADDR
gd->fb_base = CONFIG_FB_ADDR;
#else
/* reserve memory for LCD display (always full pages) */
addr = lcd_setmem(addr);
gd->fb_base = addr;
#endif /* CONFIG_FB_ADDR */
#endif /* CONFIG_LCD */
#if defined(CONFIG_VIDEO) && defined(CONFIG_8xx)
/* reserve memory for video display (always full pages) */
addr = video_setmem(addr);
gd->fb_base = addr;
#endif /* CONFIG_VIDEO */
/*
* reserve memory for U-Boot code, data & bss
* round down to next 4 kB limit
*/
addr -= len;
addr &= ~(4096 - 1);
#ifdef CONFIG_E500
/* round down to next 64 kB limit so that IVPR stays aligned */
addr &= ~(65536 - 1);
#endif
debug("Reserving %ldk for U-Boot at: %08lx\n", len >> 10, addr);
/*
* reserve memory for malloc() arena
*/
addr_sp = addr - TOTAL_MALLOC_LEN;
debug("Reserving %dk for malloc() at: %08lx\n",
TOTAL_MALLOC_LEN >> 10, addr_sp);
/*
* (permanently) allocate a Board Info struct
* and a permanent copy of the "global" data
*/
addr_sp -= sizeof(bd_t);
bd = (bd_t *) addr_sp;
memset(bd, 0, sizeof(bd_t));
gd->bd = bd;
debug("Reserving %zu Bytes for Board Info at: %08lx\n",
sizeof(bd_t), addr_sp);
addr_sp -= sizeof(gd_t);
id = (gd_t *) addr_sp;
debug("Reserving %zu Bytes for Global Data at: %08lx\n",
sizeof(gd_t), addr_sp);
/*
* Finally, we set up a new (bigger) stack.
*
* Leave some safety gap for SP, force alignment on 16 byte boundary
* Clear initial stack frame
*/
addr_sp -= 16;
addr_sp &= ~0xF;
s = (ulong *) addr_sp;
*s = 0; /* Terminate back chain */
*++s = 0; /* NULL return address */
debug("Stack Pointer at: %08lx\n", addr_sp);
/*
* Save local variables to board info struct
*/
bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */
bd->bi_memsize = gd->ram_size; /* size in bytes */
#ifdef CONFIG_SYS_SRAM_BASE
bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */
bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */
#endif
#if defined(CONFIG_8xx) || defined(CONFIG_MPC8260) || defined(CONFIG_5xx) || \
defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */
#endif
#if defined(CONFIG_MPC5xxx)
bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
#endif
#if defined(CONFIG_MPC83xx)
bd->bi_immrbar = CONFIG_SYS_IMMR;
#endif
WATCHDOG_RESET();
bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */
bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
#if defined(CONFIG_CPM2)
bd->bi_cpmfreq = gd->arch.cpm_clk;
bd->bi_brgfreq = gd->arch.brg_clk;
bd->bi_sccfreq = gd->arch.scc_clk;
bd->bi_vco = gd->arch.vco_out;
#endif /* CONFIG_CPM2 */
#if defined(CONFIG_MPC512X)
bd->bi_ipsfreq = gd->arch.ips_clk;
#endif /* CONFIG_MPC512X */
#if defined(CONFIG_MPC5xxx)
bd->bi_ipbfreq = gd->arch.ipb_clk;
bd->bi_pcifreq = gd->pci_clk;
#endif /* CONFIG_MPC5xxx */
#ifdef CONFIG_SYS_EXTBDINFO
strncpy((char *) bd->bi_s_version, "1.2", sizeof(bd->bi_s_version));
strncpy((char *) bd->bi_r_version, U_BOOT_VERSION,
sizeof(bd->bi_r_version));
bd->bi_procfreq = gd->cpu_clk; /* Processor Speed, In Hz */
bd->bi_plb_busfreq = gd->bus_clk;
#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
bd->bi_pci_busfreq = get_PCI_freq();
bd->bi_opbfreq = get_OPB_freq();
#elif defined(CONFIG_XILINX_405)
bd->bi_pci_busfreq = get_PCI_freq();
#endif
#endif
debug("New Stack Pointer is: %08lx\n", addr_sp);
WATCHDOG_RESET();
gd->relocaddr = addr; /* Store relocation addr, useful for debug */
memcpy(id, (void *) gd, sizeof(gd_t));
relocate_code(addr_sp, id, addr);
/* NOTREACHED - relocate_code() does not return */
}