/*
* PL011 single character TX.
*/
void __init arch_defterm_early_putc(u8 ch)
{
while (vmm_readl(early_base + UART_PL011_FR) & UART_PL011_FR_TXFF)
;
vmm_writeb(ch, early_base + UART_PL011_DR);
while (vmm_readl(early_base + UART_PL011_FR) & UART_PL011_FR_BUSY)
;
}
void *memset_io(void *dest, int c, size_t count)
{
u8 *dst8 = (u8 *) dest;
u8 ch = (u8) c;
if (count & 1) {
vmm_writeb(ch, &dst8[0]);
dst8 += 1;
}
count /= 2;
while (count--) {
vmm_writeb(ch, &dst8[0]);
vmm_writeb(ch, &dst8[1]);
dst8 += 2;
}
return dest;
}
void __init arch_defterm_early_putc(u8 ch)
{
struct uart_zynq *reg = (struct uart_zynq *)early_base;
/* Wait until FIFO is not empty */
while (!(vmm_readw(®->channel_sts) & ZYNQ_UART_SR_TXEMPTY)) ;
/* Send the character */
vmm_writeb(ch, (void *)®->tx_rx_fifo);
}
void __init arch_defterm_early_putc(u8 ch)
{
void *io = early_base + BCM283X_MU_IO;
void *lsr = early_base + BCM283X_MU_LSR;
/* Wait until FIFO is not empty */
while (!(vmm_readw(lsr) & BCM283X_MU_LSR_TX_EMPTY)) ;
/* Send the character */
vmm_writeb(ch, io);
}
void *memcpy_toio(void *dest, const void *src, size_t count)
{
u8 *dst8 = (u8 *) dest;
u8 *src8 = (u8 *) src;
if (count & 1) {
vmm_writeb(src8[0], &dst8[0]);
dst8 += 1;
src8 += 1;
}
count /= 2;
while (count--) {
vmm_writeb(src8[0], &dst8[0]);
vmm_writeb(src8[1], &dst8[1]);
dst8 += 2;
src8 += 2;
}
return dest;
}
void __init arch_defterm_early_putc(u8 ch)
{
u16 scfsr;
/* Wait until FIFO is not empty */
while (!(vmm_readw(early_base + SCIF_SCFSR) & SCFSR_TEND)) ;
/* Send the character */
vmm_writeb(ch, early_base + SCIF_SCFTDR);
/* Clear required TX flags */
scfsr = vmm_readw(early_base + SCIF_SCFSR);
scfsr &= ~(SCFSR_TEND | SCFSR_TDFE);
vmm_writew(scfsr, early_base + SCIF_SCFSR);
}
/*
* Set the executing CPUs power mode as defined. This will be in
* preparation for it executing a WFI instruction.
*
* This function must be called with preemption disabled, and as it
* has the side effect of disabling coherency, caches must have been
* flushed. Interrupts must also have been disabled.
*/
int scu_power_mode(void *scu_base, u32 mode)
{
u32 val, cpu;
cpu = vmm_smp_processor_id();
if (mode > SCU_PM_POWEROFF || mode == SCU_PM_EINVAL || cpu > 3) {
return VMM_EFAIL;
}
val = vmm_readb(scu_base + SCU_CPU_STATUS + cpu) & ~0x03;
val |= mode;
vmm_writeb(val, scu_base + SCU_CPU_STATUS + cpu);
return VMM_OK;
}
/*
* 8250/16550 (8-bit aligned registers) single character TX.
*/
void __init arch_defterm_early_putc(u8 ch)
{
while (!(vmm_readb(early_base + UART_LSR_OFFSET) & UART_LSR_THRE))
;
vmm_writeb(ch, early_base + UART_THR_OFFSET);
}
