void govw_reg_dump(void)
{
auto_pll_divisor(DEV_GOVW,CLK_ENABLE,0,0);
DPRINT("========== GOVW register dump ==========\n");
vpp_reg_dump(REG_GOVW_BEGIN,REG_GOVW_END-REG_GOVW_BEGIN);
DPRINT("GOVW enable %d\n",vppif_reg32_read(GOVW_HD_MIF_ENABLE));
DPRINT("color mode %s\n",vpp_colfmt_str[govw_get_color_format()]);
DPRINT("Y addr 0x%x,C addr 0x%x\n",vppif_reg32_in(REG_GOVW_HD_YSA),vppif_reg32_in(REG_GOVW_HD_CSA));
DPRINT("Y width %d,fb width %d\n",vppif_reg32_read(GOVW_HD_YPXLWID),vppif_reg32_read(GOVW_HD_YBUFWID));
DPRINT("C width %d,fb width %d\n",vppif_reg32_read(GOVW_HD_CPXLWID),vppif_reg32_read(GOVW_HD_CBUFWID));
DPRINT("---------- GOVW TG ----------\n");
DPRINT("TG enable %d, wait ready enable %d\n",vppif_reg32_read(GOVW_TG_ENABLE),vppif_reg32_read(GOVW_TG_WATCHDOG_ENABLE));
DPRINT("clk %d,Read cyc %d\n",vpp_get_base_clock(VPP_MOD_GOVW),vppif_reg32_read(GOVW_TG_RDCYC));
DPRINT("H total %d, beg %d, end %d\n",vppif_reg32_read(GOVW_TG_H_ALLPIXEL),
vppif_reg32_read(GOVW_TG_H_ACTBG),vppif_reg32_read(GOVW_TG_H_ACTEND));
DPRINT("V total %d, beg %d, end %d\n",vppif_reg32_read(GOVW_TG_V_ALLLINE),
vppif_reg32_read(GOVW_TG_V_ACTBG),vppif_reg32_read(GOVW_TG_V_ACTEND));
DPRINT("VBIE %d,PVBI %d\n",vppif_reg32_read(GOVW_TG_VBIE),vppif_reg32_read(GOVW_TG_PVBI));
DPRINT("Watch dog 0x%x\n",vppif_reg32_read(GOVW_TG_WATCHDOG_VALUE));
DPRINT("INT MIF C err %d,Y err %d,TG err %d\n",vppif_reg32_read(GOVW_INT_MIFCERR_ENABLE),
vppif_reg32_read(GOVW_INT_MIFYERR_ENABLE),vppif_reg32_read(GOVW_INT_TGERR_ENABLE));
auto_pll_divisor(DEV_GOVW,CLK_DISABLE,0,0);
}
void sclr_set_fb_addr(U32 y_addr, U32 c_addr)
{
unsigned int line_y,line_c;
unsigned int offset_y,offset_c;
unsigned int pre_y,pre_c;
DBGMSG("y_addr:0x%08x, c_addr:0x%08x\n",y_addr,c_addr);
offset_y = offset_c = 0;
line_y = line_c = vppif_reg32_read(SCLR_YBUFWID);
switch(sclr_get_color_format()){
case VDO_COL_FMT_YUV420:
offset_c /= 2;
line_c = 0;
break;
case VDO_COL_FMT_YUV422H:
break;
case VDO_COL_FMT_ARGB:
offset_y *= 4;
line_y *= 4;
break;
case VDO_COL_FMT_RGB_565:
offset_y *= 2;
line_y *= 2;
break;
default:
offset_c *= 2;
line_c *= 2;
break;
}
pre_y = vppif_reg32_in(REG_SCLR_YSA);
pre_c = vppif_reg32_in(REG_SCLR_CSA);
vppif_reg32_out(REG_SCLR_YSA,y_addr+offset_y);
vppif_reg32_out(REG_SCLR_CSA,c_addr+offset_c);
switch(scl_get_filter_mode()){
default:
case VPP_FILTER_SCALE:
case VPP_FILTER_FIELD_DEFLICKER:
vppif_reg32_out(REG_SCLR_YSA2,y_addr+offset_y+line_y);
vppif_reg32_out(REG_SCLR_CSA2,c_addr+offset_c+line_c);
break;
case VPP_FILTER_DEBLOCK:
vppif_reg32_out(REG_SCLR_YSA2,y_addr+offset_y);
vppif_reg32_out(REG_SCLR_CSA2,c_addr+offset_c);
break;
case VPP_FILTER_FRAME_DEFLICKER:
// next frame buffer address
vppif_reg32_out(REG_SCLR_YSA2,pre_y);
vppif_reg32_out(REG_SCLR_CSA2,pre_c);
break;
}
}
/*----------------------- Module API --------------------------------------*/
void lvds_reg_dump(void)
{
int i;
DPRINT("========== LVDS register dump ==========\n");
for(i=0;i<0x18;i+=16){
DPRINT("0x%8x : 0x%08x 0x%08x 0x%08x 0x%08x\n",LVDS_BASE_ADDR+i,vppif_reg32_in(LVDS_BASE_ADDR+i),
vppif_reg32_in(LVDS_BASE_ADDR+i+4),vppif_reg32_in(LVDS_BASE_ADDR+i+8),vppif_reg32_in(LVDS_BASE_ADDR+i+12));
}
DPRINT("---------- LVDS common ----------\n");
DPRINT("test %d,dual chan %d,inv clk %d\n",vppif_reg32_read(LVDS_TEST),vppif_reg32_read(LVDS_DUAL_CHANNEL),vppif_reg32_read(LVDS_INV_CLK));
DPRINT("ldi shift left %d,IGS bpp type %d\n",vppif_reg32_read(LVDS_LDI_SHIFT_LEFT),vppif_reg32_read(LVDS_IGS_BPP_TYPE));
DPRINT("rsen %d,pll ready %d\n",vppif_reg32_read(LVDS_RSEN),vppif_reg32_read(LVDS_PLL_READY));
}
int wmt_cec_rx_data(char *buf)
{
int i, size;
unsigned int addr, reg;
addr = REG_CEC_DECODE_HEADER;
for (i = 0; i < 16; i++) {
reg = vppif_reg32_in(addr);
buf[i] = (reg & 0xFF0) >> 4;
if (reg & BIT1) /* EOM */
break;
addr += 4;
}
vppif_reg32_write(CEC_FINISH_RESET, 1);
mdelay(1);
vppif_reg32_write(CEC_FINISH_RESET, 0);
size = i + 1;
#ifdef DEBUG
DPRINT("[CEC] rx data(%d):\n", size);
for (i = 0; i < size; i++)
DPRINT(" 0x%x", buf[i]);
DPRINT("\n");
#endif
return size;
}
int wmt_cec_get_int(void)
{
int reg;
reg = vppif_reg32_in(REG_CEC_STATUS);
return reg;
}
void govm_reg_dump(void)
{
int i;
DPRINT("========== GOVM register dump ==========\n");
for(i=0;i<0xe8;i+=16){
DPRINT("0x%08x : 0x%08x 0x%08x 0x%08x 0x%08x\n",GOVM_BASE_ADDR+i,vppif_reg32_in(GOVM_BASE_ADDR+i),
vppif_reg32_in(GOVM_BASE_ADDR+i+4),vppif_reg32_in(GOVM_BASE_ADDR+i+8),vppif_reg32_in(GOVM_BASE_ADDR+i+12));
}
DPRINT("GE enable %d,VPU enable %d\n",vppif_reg32_read(GOVM_GE_SOURCE),vppif_reg32_read(GOVM_VPU_SOURCE));
DPRINT("Display coordinate (%d,%d)\n",vppif_reg32_read(GOVM_DISP_X_CR),vppif_reg32_read(GOVM_DISP_Y_CR));
DPRINT("VPU coordinate (%d,%d) - (%d,%d)\n",vppif_reg32_read(GOVM_VPU_X_STA_CR),vppif_reg32_read(GOVM_VPU_Y_STA_CR),
vppif_reg32_read(GOVM_VPU_X_END_CR),vppif_reg32_read(GOVM_VPU_Y_END_CR));
DPRINT("alpha enable %d,mode %d,A %d,B %d\n",vppif_reg32_read(GOVM_IND_MODE_ENABLE),vppif_reg32_read(GOVM_IND_MODE),
vppif_reg32_read(GOVM_IND_ALPHA_A),vppif_reg32_read(GOVM_IND_ALPHA_B));
DPRINT("color bar enable %d,mode %d,inv %d\n",vppif_reg32_read(GOVM_COLBAR_ENABLE),
vppif_reg32_read(GOVM_COLBAR_MODE),vppif_reg32_read(GOVM_COLBAR_INVERSION));
DPRINT("INT enable GOV %d\n",vppif_reg32_read(GOVM_INT_ENABLE));
DPRINT("Gamma mode %d, clamp enable %d\n",vppif_reg32_read(GOVM_GAMMA_MODE),vppif_reg32_read(GOVM_CLAMPING_ENABLE));
}
void govw_reg_dump(void)
{
int i;
printf("========== GOVW register dump ==========\n");
for(i=0;i<0xcc;i+=16){
printf("0x%8x : 0x%08x 0x%08x 0x%08x 0x%08x\n",GOVW_BASE_ADDR+i,vppif_reg32_in(GOVW_BASE_ADDR+i),
vppif_reg32_in(GOVW_BASE_ADDR+i+4),vppif_reg32_in(GOVW_BASE_ADDR+i+8),vppif_reg32_in(GOVW_BASE_ADDR+i+12));
}
printf("GOVW enable %d\n",vppif_reg32_read(GOVW_HD_MIF_ENABLE));
printf("color mode %s\n",vpp_colfmt_str[govw_get_hd_color_format()]);
printf("Y addr 0x%x,C addr 0x%x\n",vppif_reg32_in(REG_GOVW_HD_YSA),vppif_reg32_in(REG_GOVW_HD_CSA));
printf("Y width %d,fb width %d\n",vppif_reg32_read(GOVW_HD_YPXLWID),vppif_reg32_read(GOVW_HD_YBUFWID));
printf("C width %d,fb width %d\n",vppif_reg32_read(GOVW_HD_CPXLWID),vppif_reg32_read(GOVW_HD_CBUFWID));
printf("---------- GOVW TG ----------\n");
printf("TG enable %d, wait ready enable %d\n",vppif_reg32_read(GOVW_TG_ENABLE),vppif_reg32_read(GOVW_TG_WATCHDOG_ENABLE));
printf("clk %d,Read cyc %d\n",vpp_get_base_clock(VPP_PLL_B,VPP_DIV_VPP),vppif_reg32_read(GOVW_TG_RDCYC));
printf("H total %d, beg %d, end %d\n",vppif_reg32_read(GOVW_TG_H_ALLPIXEL),
vppif_reg32_read(GOVW_TG_H_ACTBG),vppif_reg32_read(GOVW_TG_H_ACTEND));
printf("V total %d, beg %d, end %d\n",vppif_reg32_read(GOVW_TG_V_ALLLINE),
vppif_reg32_read(GOVW_TG_V_ACTBG),vppif_reg32_read(GOVW_TG_V_ACTEND));
printf("VBIE %d,PVBI %d\n",vppif_reg32_read(GOVW_TG_VBIE),vppif_reg32_read(GOVW_TG_PVBI));
printf("Watch dog %d\n",vppif_reg32_read(GOVW_TG_WATCHDOG_VALUE));
printf("INT MIF C err %d,Y err %d,TG err %d\n",vppif_reg32_read(GOVW_INT_MIFCERR_ENABLE),
vppif_reg32_read(GOVW_INT_MIFYERR_ENABLE),vppif_reg32_read(GOVW_INT_TGERR_ENABLE));
}
int scl_proc_scale_complete(void *arg)
{
// DPRINT("[SCL] scl_proc_scale_complete\n");
if( vppif_reg32_read(SCL_INTSTS_TGERR) ){
DPRINT("[SCL] scale TG err 0x%x,0x%x\n",vppif_reg32_in(REG_SCL_TG_STS),vppif_reg32_in(REG_SCLW_FF_CTL));
vppif_reg32_out(REG_SCL_TG_STS+0x0,BIT0);
vppif_reg32_out(REG_SCLW_FF_CTL,0x10101);
}
scl_set_tg_enable(VPP_FLAG_DISABLE);
vppm_set_int_enable(VPP_FLAG_DISABLE,SCL_COMPLETE_INT);
sclw_set_mif_enable(VPP_FLAG_DISABLE);
sclr_set_mif_enable(VPP_FLAG_DISABLE);
sclr_set_mif2_enable(VPP_FLAG_DISABLE);
scl_set_enable(VPP_FLAG_DISABLE);
//#ifdef __KERNEL__
#if 0
INIT_WORK(&scl_proc_scale_wq, scl_proc_scale_complete_work);
schedule_work(&scl_proc_scale_wq);
#else
scl_proc_scale_complete_work(0);
#endif
return 0;
}
void scl_reg_dump(void)
{
auto_pll_divisor(DEV_SCL444U,CLK_ENABLE,0,0);
DPRINT("========== SCL register dump ==========\n");
vpp_reg_dump(REG_SCL_BASE1_BEGIN,REG_SCL_BASE1_END-REG_SCL_BASE1_BEGIN);
vpp_reg_dump(REG_SCL_BASE2_BEGIN,REG_SCL_BASE2_END-REG_SCL_BASE2_BEGIN);
DPRINT("---------- SCL scale ----------\n");
DPRINT("scale enable %d\n",vppif_reg32_read(SCL_ALU_ENABLE));
DPRINT("scale width H %d,V %d\n",vppif_reg32_read(SCL_HXWIDTH),vppif_reg32_read(SCL_VXWIDTH));
DPRINT("H scale up %d,V scale up %d\n",vppif_reg32_read(SCL_HSCLUP_ENABLE),vppif_reg32_read(SCL_VSCLUP_ENABLE));
DPRINT("H sub step %d,thr %d,step %d,sub step cnt %d,i step cnt %d\n",vppif_reg32_read(SCL_H_SUBSTEP),
vppif_reg32_read(SCL_H_THR),vppif_reg32_read(SCL_H_STEP),vppif_reg32_read(SCL_H_I_SUBSTEPCNT),vppif_reg32_read(SCL_H_I_STEPCNT));
DPRINT("V sub step %d,thr %d,step %d,sub step cnt %d,i step cnt %d\n",vppif_reg32_read(SCL_V_SUBSTEP),
vppif_reg32_read(SCL_V_THR),vppif_reg32_read(SCL_V_STEP),vppif_reg32_read(SCL_V_I_SUBSTEPCNT),vppif_reg32_read(SCL_V_I_STEPCNT));
DPRINT("---------- SCL filter ----------\n");
DPRINT("DEBLOCK %d,boundary 1st 0x%x,2nd 0x%x\n,",vppif_reg32_read(SCL_DEBLOCK_ENABLE),
vppif_reg32_read(SCL_1ST_LAYER_BOUNDARY),vppif_reg32_read(SCL_2ND_LAYER_BOUNDARY));
DPRINT("FIELD DEFLICKER %d,up %s down,thr Y %d,C %d\n",vppif_reg32_read(SCL_FIELD_DEFLICKER),vppif_reg32_read(SCL_FIELD_DEFLICKER)?"&":"or",
vppif_reg32_read(SCL_FIELD_FILTER_Y_THD),vppif_reg32_read(SCL_FIELD_FILTER_C_THD));
DPRINT("FRAME DEFLICKER %d,%s,2^%d,scene chg %d\n",vppif_reg32_read(SCL_FRAME_DEFLICKER),vppif_reg32_read(SCL_FRAME_FILTER_RGB)?"RGB":"Y",
vppif_reg32_read(SCL_FRAME_FILTER_SAMPLER),vppif_reg32_read(SCL_FR_FILTER_SCENE_CHG_THD));
DPRINT("CSC enable %d,CSC clamp %d\n",vppif_reg32_read(SCL_CSC_ENABLE),vppif_reg32_read(SCL_CSC_CLAMP_ENABLE));
DPRINT("---------- SCL TG ----------\n");
DPRINT("TG source : %s\n",(vppif_reg32_read(SCL_TG_GOVWTG_ENABLE))?"GOVW":"SCL");
DPRINT("TG enable %d, wait ready enable %d\n",vppif_reg32_read(SCL_TG_ENABLE),vppif_reg32_read(SCL_TG_WATCHDOG_ENABLE));
DPRINT("clk %d,Read cyc %d,1T %d\n",vpp_get_base_clock(VPP_MOD_SCL),vppif_reg32_read(SCL_TG_RDCYC),vppif_reg32_read(SCL_READCYC_1T));
DPRINT("H total %d, beg %d, end %d\n",vppif_reg32_read(SCL_TG_H_ALLPIXEL),vppif_reg32_read(SCL_TG_H_ACTBG),vppif_reg32_read(SCL_TG_H_ACTEND));
DPRINT("V total %d, beg %d, end %d\n",vppif_reg32_read(SCL_TG_V_ALLLINE),vppif_reg32_read(SCL_TG_V_ACTBG),vppif_reg32_read(SCL_TG_V_ACTEND));
DPRINT("VBIE %d,PVBI %d\n",vppif_reg32_read(SCL_TG_VBIE),vppif_reg32_read(SCL_TG_PVBI));
DPRINT("Watch dog 0x%x\n",vppif_reg32_read(SCL_TG_WATCHDOG_VALUE));
DPRINT("---------- SCLR FB ----------\n");
DPRINT("SCLR MIF enable %d,MIF2 enable %d\n",vppif_reg32_read(SCLR_MIF_ENABLE),vppif_reg32_read(SCLR_MIF2_ENABLE));
DPRINT("color format %s\n",vpp_colfmt_str[sclr_get_color_format()]);
DPRINT("color bar enable %d,mode %d,inv %d\n",vppif_reg32_read(SCLR_COLBAR_ENABLE),vppif_reg32_read(SCLR_COLBAR_MODE),vppif_reg32_read(SCLR_COLBAR_INVERSION));
DPRINT("sourc mode : %s,H264 %d\n",(vppif_reg32_read(SCLR_TAR_DISP_FMT))?"field":"frame",vppif_reg32_read(SCLR_MEDIAFMT_H264));
DPRINT("Y addr 0x%x, C addr 0x%x\n",vppif_reg32_in(REG_SCLR_YSA),vppif_reg32_in(REG_SCLR_CSA));
#ifdef REG_SCLR_YSA2
DPRINT("Y addr2 0x%x, C addr2 0x%x\n",vppif_reg32_in(REG_SCLR_YSA2),vppif_reg32_in(REG_SCLR_CSA2));
#endif
DPRINT("width %d, fb width %d\n",vppif_reg32_read(SCLR_YPXLWID),vppif_reg32_read(SCLR_YBUFWID));
DPRINT("H crop %d, V crop %d\n",vppif_reg32_read(SCLR_HCROP),vppif_reg32_read(SCLR_VCROP));
DPRINT("---------- SCLW FB ----------\n");
DPRINT("SCLW MIF enable %d\n",vppif_reg32_read(SCLW_MIF_ENABLE));
DPRINT("color format %s\n",vpp_colfmt_str[sclw_get_color_format()]);
DPRINT("Y addr 0x%x, C addr 0x%x\n",vppif_reg32_in(REG_SCLW_YSA),vppif_reg32_in(REG_SCLW_CSA));
DPRINT("Y width %d, fb width %d\n",vppif_reg32_read(SCLW_YPXLWID),vppif_reg32_read(SCLW_YBUFWID));
DPRINT("C width %d, fb width %d\n",vppif_reg32_read(SCLW_CPXLWID),vppif_reg32_read(SCLW_CBUFWID));
DPRINT("Y err %d, C err %d\n",vppif_reg32_read(SCLW_INTSTS_MIFYERR),vppif_reg32_read(SCLW_INTSTS_MIFCERR));
auto_pll_divisor(DEV_SCL444U,CLK_DISABLE,0,0);
}
void govw_clean_int_status(vpp_int_err_t int_sts)
{
unsigned int reg;
reg = vppif_reg32_in(REG_GOVW_INT) & 0xFF;
if (int_sts & VPP_INT_ERR_GOVW_TG) {
reg |= BIT20;
}
if (int_sts & VPP_INT_ERR_GOVW_MIFY) {
reg |= BIT19;
}
if (int_sts & VPP_INT_ERR_GOVW_MIFC) {
reg |= BIT18;
}
vppif_reg32_out(REG_GOVW_INT,reg);
}
void govw_get_hd_fb_addr(U32 * y_addr, U32 * c_addr)
{
*y_addr = vppif_reg32_in(REG_GOVW_HD_YSA);
*c_addr = vppif_reg32_in(REG_GOVW_HD_CSA);
// DBGMSG("y_addr:0x%08x, c_addr:0x%08x\n", (U32)*y_addr, (U32)*c_addr);
}
void govm_get_pip_fb_addr(unsigned int *y_addr,unsigned int *c_addr)
{
*y_addr = vppif_reg32_in(REG_GOVM_PIP_Y_ADDR);
*c_addr = vppif_reg32_in(REG_GOVM_PIP_C_ADDR);
DBGMSG("y_addr:0x%08x, c_addr:0x%08x\n", *y_addr, *c_addr);
}
vpp_int_t vppm_get_int_status(void)
{
unsigned int int_enable_reg;
unsigned int int_sts_reg;
vpp_int_t int_sts = 0;
int_enable_reg = vppif_reg32_in(REG_VPP_INTEN);
int_sts_reg = vppif_reg32_in(REG_VPP_INTSTS);
#ifdef WMT_FTBLK_SCL
if ((int_enable_reg & BIT18) && (int_sts_reg & BIT18)) {
int_sts |= VPP_INT_SCL_VBIE;
}
if ((int_enable_reg & BIT17) && (int_sts_reg & BIT17)) {
int_sts |= VPP_INT_SCL_VBIS;
}
if ((int_enable_reg & BIT16) && (int_sts_reg & BIT16)) {
int_sts |= VPP_INT_SCL_PVBI;
}
#endif
#ifdef WMT_FTBLK_GOVRH
if ((int_enable_reg & BIT10) && (int_sts_reg & BIT10)) {
int_sts |= VPP_INT_GOVRH_VBIE;
}
if ((int_enable_reg & BIT9) && (int_sts_reg & BIT9)) {
int_sts |= VPP_INT_GOVRH_VBIS;
}
if ((int_enable_reg & BIT8) && (int_sts_reg & BIT8)) {
int_sts |= VPP_INT_GOVRH_PVBI;
}
#endif
#ifdef WMT_FTBLK_GOVW
if ((int_enable_reg & BIT2) && (int_sts_reg & BIT2)) {
int_sts |= VPP_INT_GOVW_VBIE;
}
if ((int_enable_reg & BIT1) && (int_sts_reg & BIT1)) {
int_sts |= VPP_INT_GOVW_VBIS;
}
if ((int_enable_reg & BIT0) && (int_sts_reg & BIT0)) {
int_sts |= VPP_INT_GOVW_PVBI;
}
#endif
#ifdef WMT_FTBLK_DISP
if ((int_enable_reg & BIT26) && (int_sts_reg & BIT26)) {
int_sts |= VPP_INT_DISP_VBIE;
}
if ((int_enable_reg & BIT25) && (int_sts_reg & BIT25)) {
int_sts |= VPP_INT_DISP_VBIS;
}
if ((int_enable_reg & BIT24) && (int_sts_reg & BIT24)) {
int_sts |= VPP_INT_DISP_PVBI;
}
#endif
#ifdef WMT_FTBLK_VPU
if ((int_enable_reg & BIT6) && (int_sts_reg & BIT6)) {
int_sts |= VPP_INT_VPU_VBIE;
}
if ((int_enable_reg & BIT5) && (int_sts_reg & BIT5)) {
int_sts |= VPP_INT_VPU_VBIS;
}
if ((int_enable_reg & BIT4) && (int_sts_reg & BIT4)) {
int_sts |= VPP_INT_VPU_PVBI;
}
#endif
return int_sts;
}
void sclw_get_fb_addr(U32 *y_addr,U32 *c_addr)
{
*y_addr = vppif_reg32_in(REG_SCLW_YSA);
*c_addr = vppif_reg32_in(REG_SCLW_CSA);
DBGMSG("y_addr:0x%08x, c_addr:0x%08x\n", *y_addr, *c_addr);
}
