void sclr_get_fb_info(U32 * width, U32 * act_width, U32 * x_offset,U32 * y_offset)
{
*width = vppif_reg32_read(SCLR_YBUFWID);
*act_width = vppif_reg32_read(SCLR_YPXLWID);
*x_offset = vppif_reg32_read(SCLR_HCROP);
*y_offset = vppif_reg32_read(SCLR_VCROP);
}
// only one feature can work, other should be disable
void scl_set_filter_mode(vpp_filter_mode_t mode,int enable)
{
// DPRINT("%s(%d,%d)\n",__FUNCTION__,mode,enable);
if( mode != VPP_FILTER_SCALE ){
if( vppif_reg32_read(SCL_VSCLUP_ENABLE) || vppif_reg32_read(SCL_HSCLUP_ENABLE) ){
DPRINT("[SCL] *W* filter can't work w scale\n");
}
}
vppif_reg32_write(SCL_DEBLOCK_ENABLE,0);
vppif_reg32_write(SCL_FIELD_DEFLICKER,0);
vppif_reg32_write(SCL_FRAME_DEFLICKER,0);
switch( mode ){
default:
case VPP_FILTER_SCALE: // scale mode
break;
case VPP_FILTER_DEBLOCK: // deblock
vppif_reg32_write(SCL_DEBLOCK_ENABLE,enable);
break;
case VPP_FILTER_FIELD_DEFLICKER: // field deflicker
vppif_reg32_write(SCL_FIELD_DEFLICKER,enable);
break;
case VPP_FILTER_FRAME_DEFLICKER: // frame deflicker
vppif_reg32_write(SCL_FRAME_DEFLICKER,enable);
break;
}
}
void scl_suspend(int sts)
{
switch( sts ){
case 0: // disable module
vpp_mod_set_clock(VPP_MOD_SCL,VPP_FLAG_ENABLE,1);
scl_pm_enable = vppif_reg32_read(SCL_ALU_ENABLE);
vppif_reg32_write(SCL_ALU_ENABLE,0);
scl_pm_r_mif1 = vppif_reg32_read(SCLR_MIF_ENABLE);
scl_pm_r_mif2 = vppif_reg32_read(SCLR_MIF2_ENABLE);
vppif_reg32_write(SCLR_MIF_ENABLE,0);
vppif_reg32_write(SCLR_MIF2_ENABLE,0);
scl_pm_w_mif = vppif_reg32_read(SCLW_MIF_ENABLE);
vppif_reg32_write(SCLW_MIF_ENABLE,0);
break;
case 1: // disable tg
scl_pm_tg = vppif_reg32_read(SCL_TG_ENABLE);
vppif_reg32_write(SCL_TG_ENABLE,0);
break;
case 2: // backup register
p_scl->reg_bk = vpp_backup_reg(REG_SCL_BASE1_BEGIN,(REG_SCL_BASE1_END-REG_SCL_BASE1_BEGIN));
scl_pm_bk2 = vpp_backup_reg(REG_SCL_BASE2_BEGIN,(REG_SCL_BASE2_END-REG_SCL_BASE2_BEGIN));
break;
default:
break;
}
}
void govm_set_vpu_position(U32 x1, U32 y1)
{
U32 x2, y2;
x2 = x1 + vppif_reg32_read(GOVM_VPU_X_END_CR) - vppif_reg32_read(GOVM_VPU_X_STA_CR);
y2 = y1 + vppif_reg32_read(GOVM_VPU_Y_END_CR) - vppif_reg32_read(GOVM_VPU_Y_STA_CR);
govm_set_vpu_coordinate(x1, y1, x2, y2);
}
void govm_set_pip_position(unsigned int x1, unsigned int y1)
{
unsigned int x2, y2;
x2 = x1 + vppif_reg32_read(GOVM_PIP_X_END_CR) - vppif_reg32_read(GOVM_PIP_X_STA_CR);
y2 = y1 + vppif_reg32_read(GOVM_PIP_Y_END_CR) - vppif_reg32_read(GOVM_PIP_Y_STA_CR);
govm_set_pip_coordinate(x1, y1, x2, y2);
}
vdo_color_fmt govm_get_pip_color_format(void)
{
if( vppif_reg32_read(GOVM_PIP_COLFMT_RGB) )
return VDO_COL_FMT_ARGB;
if( vppif_reg32_read(GOVM_PIP_COLFMT_444) ){
return VDO_COL_FMT_YUV444;
}
if( vppif_reg32_read(GOVM_PIP_COLFMT_422) ){
return VDO_COL_FMT_YUV420;
}
return VDO_COL_FMT_YUV422H;
}
void govw_get_timing(vpp_clock_t * p_timing)
{
p_timing->read_cycle = vppif_reg32_read(GOVW_TG_RDCYC);
p_timing->total_pixel_of_line = vppif_reg32_read(GOVW_TG_H_ALLPIXEL);
p_timing->begin_pixel_of_active = vppif_reg32_read(GOVW_TG_H_ACTBG);
p_timing->end_pixel_of_active = vppif_reg32_read(GOVW_TG_H_ACTEND);
p_timing->total_line_of_frame = vppif_reg32_read(GOVW_TG_V_ALLLINE);
p_timing->begin_line_of_active = vppif_reg32_read(GOVW_TG_V_ACTBG);
p_timing->end_line_of_active = vppif_reg32_read(GOVW_TG_V_ACTEND);
p_timing->line_number_between_VBIS_VBIE = vppif_reg32_read(GOVW_TG_VBIE);
p_timing->line_number_between_PVBI_VBIS = vppif_reg32_read(GOVW_TG_PVBI);
}
vdo_color_fmt sclw_get_color_format(void)
{
if( vppif_reg32_read(SCLW_COLFMT_RGB) ){
switch(vppif_reg32_read(SCL_IGS_MODE)){
case 0: return VDO_COL_FMT_ARGB;
case 1: return VDO_COL_FMT_RGB_1555;
case 2: return VDO_COL_FMT_RGB_666;
case 3: return VDO_COL_FMT_RGB_565;
}
}
if( vppif_reg32_read(SCLW_COLFMT_YUV) ){
return VDO_COL_FMT_YUV422H;
}
return VDO_COL_FMT_YUV444;
}
void govw_set_timing(vpp_clock_t *timing,unsigned int pixel_clock)
{
int tg_bk;
DBG_MSG("govw set timing\n");
timing->read_cycle = ( timing->read_cycle < WMT_GOVW_RCYC_MIN )? WMT_GOVW_RCYC_MIN:timing->read_cycle;
timing->read_cycle = ( timing->read_cycle > 255 )? 0xFF:timing->read_cycle;
tg_bk = vppif_reg32_read(GOVW_TG_ENABLE);
vppif_reg32_write(GOVW_TG_ENABLE,0);
vppif_reg32_write(GOVW_TG_RDCYC,timing->read_cycle);
vppif_reg32_write(GOVW_TG_H_ALLPIXEL,timing->total_pixel_of_line);
vppif_reg32_write(GOVW_TG_H_ACTBG,timing->begin_pixel_of_active);
vppif_reg32_write(GOVW_TG_H_ACTEND,timing->end_pixel_of_active);
vppif_reg32_write(GOVW_TG_V_ALLLINE,timing->total_line_of_frame);
vppif_reg32_write(GOVW_TG_V_ACTBG,timing->begin_line_of_active);
vppif_reg32_write(GOVW_TG_V_ACTEND,timing->end_line_of_active);
vppif_reg32_write(GOVW_TG_VBIE,timing->line_number_between_VBIS_VBIE);
//vppif_reg32_write(GOVW_TG_PVBI,timing->line_number_between_PVBI_VBIS);
vppif_reg32_write(GOVW_TG_PVBI,10);
vppif_reg32_write(GOVW_TG_ENABLE,tg_bk);
DBG_DETAIL("H beg %d,end %d,total %d\n",
timing->begin_pixel_of_active,timing->end_pixel_of_active,timing->total_pixel_of_line);
DBG_DETAIL("V beg %d,end %d,total %d\n",
timing->begin_line_of_active,timing->end_line_of_active,timing->total_line_of_frame);
}
vdo_color_fmt sclr_get_color_format(void)
{
switch( vppif_reg32_read(SCLR_RGB_MODE) ){
case 0x1: return VDO_COL_FMT_RGB_565;
case 0x3: return VDO_COL_FMT_ARGB;
default:
break;
}
switch( vppif_reg32_read(SCLR_COLFMT_YUV) ){
case 0: return VDO_COL_FMT_YUV422H;
case 1: return VDO_COL_FMT_YUV420;
case 2: return VDO_COL_FMT_YUV444;
default: break;
}
return VDO_COL_FMT_YUV444;
}
vpp_filter_mode_t scl_get_filter_mode(void)
{
if( vppif_reg32_read(SCL_VSCLUP_ENABLE) || vppif_reg32_read(SCL_HSCLUP_ENABLE) ){
return VPP_FILTER_SCALE;
}
if( vppif_reg32_read(SCL_DEBLOCK_ENABLE) )
return VPP_FILTER_DEBLOCK;
if( vppif_reg32_read(SCL_FIELD_DEFLICKER) )
return VPP_FILTER_FIELD_DEFLICKER;
if( vppif_reg32_read(SCL_FRAME_DEFLICKER) )
return VPP_FILTER_FRAME_DEFLICKER;
return VPP_FILTER_SCALE;
}
vpp_mod_t scl_get_timing_master(void)
{
if( vppif_reg32_read(SCL_TG_GOVWTG_ENABLE) ){
return VPP_MOD_GOVW;
}
return VPP_MOD_SCL;
}
vpp_int_err_t govw_get_int_status(void)
{
vpp_int_err_t int_sts;
int_sts = 0;
if (vppif_reg32_read(GOVW_INTSTS_TGERR)) {
int_sts |= VPP_INT_ERR_GOVW_TG;
}
if (vppif_reg32_read(GOVW_INTSTS_MIFYERR)) {
int_sts |= VPP_INT_ERR_GOVW_MIFY;
}
if (vppif_reg32_read(GOVW_INTSTS_MIFCERR)) {
int_sts |= VPP_INT_ERR_GOVW_MIFC;
}
return int_sts;
}
void scl_set_scale(unsigned int SRC_W,unsigned int SRC_H,unsigned int DST_W,unsigned int DST_H)
{
int h_scale_up;
int v_scale_up;
DBGMSG("[SCL] src(%dx%d),dst(%dx%d)\n",SRC_W,SRC_H,DST_W,DST_H);
h_scale_up = ( DST_W > SRC_W )? 1:0;
v_scale_up = ( DST_H > SRC_H )? 1:0;
if( ((DST_W / SRC_W) >= 32) || ((DST_W / SRC_W) < 1/32) ){
DBGMSG("*W* SCL H scale rate invalid\n");
}
if( ((DST_H / SRC_H) >= 32) || ((DST_H / SRC_H) < 1/32) ){
DBGMSG("*W* SCL V scale rate invalid\n");
}
// DBGMSG("scale H %d,V %d\n",h_scale_up,v_scale_up);
sclr_set_mif2_enable(VPP_FLAG_DISABLE);
scl_set_scale_PP(SRC_W,DST_W,1);
if( h_scale_up ){ // max 32
vppif_reg32_out(REG_SCL_HSCL_TB0,3);
vppif_reg32_out(REG_SCL_HPTR,0);
vppif_reg32_write(SCL_BILINEAR_H,0);
}
else { // min 1/32
vppif_reg32_out(REG_SCL_HSCL_TB0,1);
scl_set_scale_RT(SRC_W,DST_W,1);
}
scl_set_scale_PP(SRC_H,DST_H,0);
if( v_scale_up ){ // max 32
vppif_reg32_out(REG_SCL_VSCL_TB0,3);
vppif_reg32_out(REG_SCL_VPTR,0);
}
else { // min 1/16
scl_set_scale_RT(SRC_H,DST_H,0);
// mif2 enable in real quality mode,only mif1 in SCL recursive mode
if( vppif_reg32_read(SCL_TG_GOVWTG_ENABLE) && (vppif_reg32_read(SCL_SCLDW_METHOD)==0)){
sclr_set_mif2_enable(VPP_FLAG_ENABLE);
}
}
scl_set_scale_enable(v_scale_up, h_scale_up);
}
vdo_color_fmt govw_get_hd_color_format(void)
{
if( vppif_reg32_read(GOVW_COLFMT_RGB) ){
switch( vppif_reg32_read(GOVW_RGB_MODE) ){
default:
case 0: return VDO_COL_FMT_ARGB;
case 1: return VDO_COL_FMT_RGB_1555;
case 2: return VDO_COL_FMT_RGB_666;
case 3: return VDO_COL_FMT_RGB_565;
}
return VDO_COL_FMT_ARGB;
}
if( !vppif_reg32_read(GOVW_HD_COLFMT) ){
return VDO_COL_FMT_YUV422H;
}
return VDO_COL_FMT_YUV444;
}
void govw_suspend(int sts)
{
switch( sts ){
case 0: // disable module
govw_pm_enable = vppif_reg32_read(GOVW_HD_MIF_ENABLE);
vppif_reg32_write(GOVW_HD_MIF_ENABLE,0);
break;
case 1: // disable tg
govw_pm_tg = vppif_reg32_read(GOVW_TG_ENABLE);
vppif_reg32_write(GOVW_TG_ENABLE,0);
break;
case 2: // backup register
p_govw->reg_bk = vpp_backup_reg(GOVW_BASE_ADDR+0x00,0xCC); /* 0x00 - 0xCC */
break;
default:
break;
}
}
void govw_suspend(int sts)
{
switch( sts ){
case 0: // disable module
vpp_mod_set_clock(VPP_MOD_GOVW,VPP_FLAG_ENABLE,1);
govw_pm_tg = vppif_reg32_read(GOVW_TG_ENABLE);
vppif_reg32_write(GOVW_TG_ENABLE,0);
govw_pm_enable = vppif_reg32_read(GOVW_HD_MIF_ENABLE);
vppif_reg32_write(GOVW_HD_MIF_ENABLE,0);
break;
case 1: // disable tg
break;
case 2: // backup register
p_govw->reg_bk = vpp_backup_reg(REG_GOVW_BEGIN,(REG_GOVW_END-REG_GOVW_BEGIN));
break;
default:
break;
}
}
void sclr_set_fb_addr(U32 y_addr, U32 c_addr)
{
unsigned int line_y,line_c;
unsigned int offset_y,offset_c;
unsigned int pre_y,pre_c;
DBGMSG("y_addr:0x%08x, c_addr:0x%08x\n",y_addr,c_addr);
offset_y = offset_c = 0;
line_y = line_c = vppif_reg32_read(SCLR_YBUFWID);
switch(sclr_get_color_format()){
case VDO_COL_FMT_YUV420:
offset_c /= 2;
line_c = 0;
break;
case VDO_COL_FMT_YUV422H:
break;
case VDO_COL_FMT_ARGB:
offset_y *= 4;
line_y *= 4;
break;
case VDO_COL_FMT_RGB_565:
offset_y *= 2;
line_y *= 2;
break;
default:
offset_c *= 2;
line_c *= 2;
break;
}
pre_y = vppif_reg32_in(REG_SCLR_YSA);
pre_c = vppif_reg32_in(REG_SCLR_CSA);
vppif_reg32_out(REG_SCLR_YSA,y_addr+offset_y);
vppif_reg32_out(REG_SCLR_CSA,c_addr+offset_c);
switch(scl_get_filter_mode()){
default:
case VPP_FILTER_SCALE:
case VPP_FILTER_FIELD_DEFLICKER:
vppif_reg32_out(REG_SCLR_YSA2,y_addr+offset_y+line_y);
vppif_reg32_out(REG_SCLR_CSA2,c_addr+offset_c+line_c);
break;
case VPP_FILTER_DEBLOCK:
vppif_reg32_out(REG_SCLR_YSA2,y_addr+offset_y);
vppif_reg32_out(REG_SCLR_CSA2,c_addr+offset_c);
break;
case VPP_FILTER_FRAME_DEFLICKER:
// next frame buffer address
vppif_reg32_out(REG_SCLR_YSA2,pre_y);
vppif_reg32_out(REG_SCLR_CSA2,pre_c);
break;
}
}
void govw_set_tg_enable(vpp_flag_t enable)
{
vppif_reg32_write(GOVW_TG_ENABLE, enable);
if( !enable ){
govw_set_reg_level(VPP_REG_LEVEL_2);
while(vppif_reg32_read(GOVW_TG_ENABLE)){ // wait govw tg off ( hw should stop in frame end )
mdelay(1);
}
govw_set_reg_level(VPP_REG_LEVEL_1);
}
// DPRINT("[GOVW] tg enable %d\n",enable);
}
vpp_path_t govm_get_in_path(void)
{
vpp_path_t ret;
ret = 0;
//#ifdef WMT_FTBLK_SCL
if (vppif_reg32_read(GOVM_VPU_SOURCE)){
ret |= VPP_PATH_GOVM_IN_VPU;
}
//#endif
#ifdef WMT_FTBLK_GE
if (vppif_reg32_read(GOVM_GE_SOURCE)){
ret |= VPP_PATH_GOVM_IN_GE;
}
#endif
#ifdef WMT_FTBLK_PIP
if (vppif_reg32_read(GOVM_PIP_SOURCE)){
ret |= VPP_PATH_GOVM_IN_PIP;
}
#endif
return ret;
}
/*---------------------------- CEC HAL --------------------------------------*/
void wmt_cec_tx_data(char *buf, int size)
{
int i;
unsigned int addr, reg;
int wait_idle;
#ifdef DEBUG
DPRINT("[CEC] tx data(%d):", size);
for (i = 0; i < size; i++)
DPRINT(" 0x%x", buf[i]);
DPRINT("\n");
#endif
if (size > 16) {
DPRINT("[CEC] *W* size max 16\n");
return;
}
wait_idle = 0;
while (vppif_reg32_read(CEC_WR_START)) { /* wait idle */
if (wait_idle >= 10) {
DPRINT("[CEC] wait idle timeout\n");
return;
}
wait_idle++;
mdelay(10);
return;
}
addr = REG_CEC_ENCODE_HEADER;
for (i = 0; i < size; i++) {
reg = (buf[i] << 4) + 0x1;
if (i == (size - 1))
reg |= BIT1;
vppif_reg32_out(addr, reg);
#ifdef DEBUG
DPRINT("[CEC] wr 0x%x = 0x%x\n", addr, reg);
#endif
addr += 4;
}
vppif_reg32_write(CEC_WR_NUM, (size * 10) + 0x1);
vppif_reg32_write(CEC_WR_START, 1);
}
/*----------------------- Module API --------------------------------------*/
void lvds_reg_dump(void)
{
int i;
DPRINT("========== LVDS register dump ==========\n");
for(i=0;i<0x18;i+=16){
DPRINT("0x%8x : 0x%08x 0x%08x 0x%08x 0x%08x\n",LVDS_BASE_ADDR+i,vppif_reg32_in(LVDS_BASE_ADDR+i),
vppif_reg32_in(LVDS_BASE_ADDR+i+4),vppif_reg32_in(LVDS_BASE_ADDR+i+8),vppif_reg32_in(LVDS_BASE_ADDR+i+12));
}
DPRINT("---------- LVDS common ----------\n");
DPRINT("test %d,dual chan %d,inv clk %d\n",vppif_reg32_read(LVDS_TEST),vppif_reg32_read(LVDS_DUAL_CHANNEL),vppif_reg32_read(LVDS_INV_CLK));
DPRINT("ldi shift left %d,IGS bpp type %d\n",vppif_reg32_read(LVDS_LDI_SHIFT_LEFT),vppif_reg32_read(LVDS_IGS_BPP_TYPE));
DPRINT("rsen %d,pll ready %d\n",vppif_reg32_read(LVDS_RSEN),vppif_reg32_read(LVDS_PLL_READY));
}
vpp_int_err_t govm_get_int_status(void)
{
vpp_int_err_t int_sts;
int_sts = 0;
if (vppif_reg32_read(GOVM_INTSTS_GOVM_STATUS)){
if( vppif_reg32_read(GOVM_INTSTS_VPU_READY) == 0 ){
int_sts |= VPP_INT_ERR_GOVM_VPU;
}
if( vppif_reg32_read(GOVM_INTSTS_GE_READY) == 0 ){
int_sts |= VPP_INT_ERR_GOVM_GE;
}
vppif_reg8_out(REG_GOVM_INT+0x0,BIT0);
}
#ifdef WMT_FTBLK_SPU
if( vppif_reg32_read(GOVM_INTSTS_SPU_READY) == 0 ){
int_sts |= VPP_INT_ERR_GOVM_SPU;
}
#endif
#ifdef WMT_FTBLK_PIP
if (vppif_reg32_read(GOVM_INT_PIP_ERR)){
if( vppif_reg32_read(GOVM_INTSTS_PIP_READY) == 0 ){
int_sts |= VPP_INT_ERR_GOVM_PIP;
}
}
if( vppif_reg32_read(GOVM_INT_PIP_Y_ERR) ){
int_sts |= VPP_INT_ERR_PIP_Y;
}
if( vppif_reg32_read(GOVM_INT_PIP_C_ERR) ){
int_sts |= VPP_INT_ERR_PIP_C;
}
#endif
return int_sts;
}
int scl_proc_scale_complete(void *arg)
{
// DPRINT("[SCL] scl_proc_scale_complete\n");
if( vppif_reg32_read(SCL_INTSTS_TGERR) ){
DPRINT("[SCL] scale TG err 0x%x,0x%x\n",vppif_reg32_in(REG_SCL_TG_STS),vppif_reg32_in(REG_SCLW_FF_CTL));
vppif_reg32_out(REG_SCL_TG_STS+0x0,BIT0);
vppif_reg32_out(REG_SCLW_FF_CTL,0x10101);
}
scl_set_tg_enable(VPP_FLAG_DISABLE);
vppm_set_int_enable(VPP_FLAG_DISABLE,SCL_COMPLETE_INT);
sclw_set_mif_enable(VPP_FLAG_DISABLE);
sclr_set_mif_enable(VPP_FLAG_DISABLE);
sclr_set_mif2_enable(VPP_FLAG_DISABLE);
scl_set_enable(VPP_FLAG_DISABLE);
//#ifdef __KERNEL__
#if 0
INIT_WORK(&scl_proc_scale_wq, scl_proc_scale_complete_work);
schedule_work(&scl_proc_scale_wq);
#else
scl_proc_scale_complete_work(0);
#endif
return 0;
}
vpp_int_err_t scl_get_int_status(void)
{
vpp_int_err_t int_sts;
int_sts = 0;
if (vppif_reg32_read(SCL_INTSTS_TGERR))
int_sts |= VPP_INT_ERR_SCL_TG;
if (vppif_reg32_read(SCLR_INTSTS_R1MIFERR))
int_sts |= VPP_INT_ERR_SCLR1_MIF;
if (vppif_reg32_read(SCLR_INTSTS_R2MIFERR))
int_sts |= VPP_INT_ERR_SCLR2_MIF;
if (vppif_reg32_read(SCLW_INTSTS_MIFRGBERR))
int_sts |= VPP_INT_ERR_SCLW_MIFRGB;
if (vppif_reg32_read(SCLW_INTSTS_MIFYERR))
int_sts |= VPP_INT_ERR_SCLW_MIFY;
if (vppif_reg32_read(SCLW_INTSTS_MIFCERR))
int_sts |= VPP_INT_ERR_SCLW_MIFC;
return int_sts;
}
void govm_get_pip_fb_width(unsigned int *width,unsigned int *buf_width)
{
*width = vppif_reg32_read(GOVM_PIP_XWIDTH);
*buf_width = vppif_reg32_read(GOVM_PIP_FBUF_WIDTH);
}
void govw_reg_dump(void)
{
int i;
printf("========== GOVW register dump ==========\n");
for(i=0;i<0xcc;i+=16){
printf("0x%8x : 0x%08x 0x%08x 0x%08x 0x%08x\n",GOVW_BASE_ADDR+i,vppif_reg32_in(GOVW_BASE_ADDR+i),
vppif_reg32_in(GOVW_BASE_ADDR+i+4),vppif_reg32_in(GOVW_BASE_ADDR+i+8),vppif_reg32_in(GOVW_BASE_ADDR+i+12));
}
printf("GOVW enable %d\n",vppif_reg32_read(GOVW_HD_MIF_ENABLE));
printf("color mode %s\n",vpp_colfmt_str[govw_get_hd_color_format()]);
printf("Y addr 0x%x,C addr 0x%x\n",vppif_reg32_in(REG_GOVW_HD_YSA),vppif_reg32_in(REG_GOVW_HD_CSA));
printf("Y width %d,fb width %d\n",vppif_reg32_read(GOVW_HD_YPXLWID),vppif_reg32_read(GOVW_HD_YBUFWID));
printf("C width %d,fb width %d\n",vppif_reg32_read(GOVW_HD_CPXLWID),vppif_reg32_read(GOVW_HD_CBUFWID));
printf("---------- GOVW TG ----------\n");
printf("TG enable %d, wait ready enable %d\n",vppif_reg32_read(GOVW_TG_ENABLE),vppif_reg32_read(GOVW_TG_WATCHDOG_ENABLE));
printf("clk %d,Read cyc %d\n",vpp_get_base_clock(VPP_PLL_B,VPP_DIV_VPP),vppif_reg32_read(GOVW_TG_RDCYC));
printf("H total %d, beg %d, end %d\n",vppif_reg32_read(GOVW_TG_H_ALLPIXEL),
vppif_reg32_read(GOVW_TG_H_ACTBG),vppif_reg32_read(GOVW_TG_H_ACTEND));
printf("V total %d, beg %d, end %d\n",vppif_reg32_read(GOVW_TG_V_ALLLINE),
vppif_reg32_read(GOVW_TG_V_ACTBG),vppif_reg32_read(GOVW_TG_V_ACTEND));
printf("VBIE %d,PVBI %d\n",vppif_reg32_read(GOVW_TG_VBIE),vppif_reg32_read(GOVW_TG_PVBI));
printf("Watch dog %d\n",vppif_reg32_read(GOVW_TG_WATCHDOG_VALUE));
printf("INT MIF C err %d,Y err %d,TG err %d\n",vppif_reg32_read(GOVW_INT_MIFCERR_ENABLE),
vppif_reg32_read(GOVW_INT_MIFYERR_ENABLE),vppif_reg32_read(GOVW_INT_TGERR_ENABLE));
}
void govw_get_hd_width(U32 *width,U32 *fb_width)
{
*width = vppif_reg32_read(GOVW_HD_YPXLWID);
*fb_width = vppif_reg32_read(GOVW_HD_YBUFWID);
}
void govw_reg_dump(void)
{
auto_pll_divisor(DEV_GOVW,CLK_ENABLE,0,0);
DPRINT("========== GOVW register dump ==========\n");
vpp_reg_dump(REG_GOVW_BEGIN,REG_GOVW_END-REG_GOVW_BEGIN);
DPRINT("GOVW enable %d\n",vppif_reg32_read(GOVW_HD_MIF_ENABLE));
DPRINT("color mode %s\n",vpp_colfmt_str[govw_get_color_format()]);
DPRINT("Y addr 0x%x,C addr 0x%x\n",vppif_reg32_in(REG_GOVW_HD_YSA),vppif_reg32_in(REG_GOVW_HD_CSA));
DPRINT("Y width %d,fb width %d\n",vppif_reg32_read(GOVW_HD_YPXLWID),vppif_reg32_read(GOVW_HD_YBUFWID));
DPRINT("C width %d,fb width %d\n",vppif_reg32_read(GOVW_HD_CPXLWID),vppif_reg32_read(GOVW_HD_CBUFWID));
DPRINT("---------- GOVW TG ----------\n");
DPRINT("TG enable %d, wait ready enable %d\n",vppif_reg32_read(GOVW_TG_ENABLE),vppif_reg32_read(GOVW_TG_WATCHDOG_ENABLE));
DPRINT("clk %d,Read cyc %d\n",vpp_get_base_clock(VPP_MOD_GOVW),vppif_reg32_read(GOVW_TG_RDCYC));
DPRINT("H total %d, beg %d, end %d\n",vppif_reg32_read(GOVW_TG_H_ALLPIXEL),
vppif_reg32_read(GOVW_TG_H_ACTBG),vppif_reg32_read(GOVW_TG_H_ACTEND));
DPRINT("V total %d, beg %d, end %d\n",vppif_reg32_read(GOVW_TG_V_ALLLINE),
vppif_reg32_read(GOVW_TG_V_ACTBG),vppif_reg32_read(GOVW_TG_V_ACTEND));
DPRINT("VBIE %d,PVBI %d\n",vppif_reg32_read(GOVW_TG_VBIE),vppif_reg32_read(GOVW_TG_PVBI));
DPRINT("Watch dog 0x%x\n",vppif_reg32_read(GOVW_TG_WATCHDOG_VALUE));
DPRINT("INT MIF C err %d,Y err %d,TG err %d\n",vppif_reg32_read(GOVW_INT_MIFCERR_ENABLE),
vppif_reg32_read(GOVW_INT_MIFYERR_ENABLE),vppif_reg32_read(GOVW_INT_TGERR_ENABLE));
auto_pll_divisor(DEV_GOVW,CLK_DISABLE,0,0);
}
/*---------------------------- CEC API --------------------------------------*/
void wmt_cec_reg_dump(void)
{
DPRINT("========== CEC register dump ==========\n");
vpp_reg_dump(REG_CEC_BEGIN, REG_CEC_END - REG_CEC_BEGIN);
DPRINT("---------- CEC Tx ----------\n");
DPRINT("wr start %d,wr num %d\n",
vppif_reg32_read(CEC_WR_START),
vppif_reg32_read(CEC_WR_NUM));
DPRINT("wr header ack %d,EOM %d,data 0x%x\n",
vppif_reg32_read(CEC_WR_HEADER_ACK),
vppif_reg32_read(CEC_WR_HEADER_EOM),
vppif_reg32_read(CEC_WR_HEADER_DATA));
DPRINT("wr data ack %d,EOM %d,data 0x%x\n",
vppif_reg32_read(CEC_WR_DATA_ACK),
vppif_reg32_read(CEC_WR_DATA_EOM),
vppif_reg32_read(CEC_WR_DATA));
DPRINT("finish reset %d,wr retry %d\n",
vppif_reg32_read(CEC_FINISH_RESET),
vppif_reg32_read(CEC_WR_RETRY));
DPRINT("---------- CEC Rx ----------\n");
DPRINT("rd start %d,all ack %d,finish %d\n",
vppif_reg32_read(CEC_RD_START),
vppif_reg32_read(CEC_RD_ALL_ACK),
vppif_reg32_read(CEC_RD_FINISH));
DPRINT("rd header ack %d,EOM %d,data 0x%x\n",
vppif_reg32_read(CEC_RD_HEADER_ACK),
vppif_reg32_read(CEC_RD_HEADER_ACK),
vppif_reg32_read(CEC_RD_HEADER_DATA));
DPRINT("rd data ack %d,EOM %d,data 0x%x\n",
vppif_reg32_read(CEC_RD_DATA_ACK),
vppif_reg32_read(CEC_RD_DATA_EOM),
vppif_reg32_read(CEC_RD_DATA));
DPRINT("---------- Logical addr ----------\n");
DPRINT("addr1 0x%x,valid %d\n",
vppif_reg32_read(CEC_LOGICAL_ADDR1),
vppif_reg32_read(CEC_ADDR_VALID1));
DPRINT("addr2 0x%x,valid %d\n",
vppif_reg32_read(CEC_LOGICAL_ADDR2),
vppif_reg32_read(CEC_ADDR_VALID2));
DPRINT("addr3 0x%x,valid %d\n",
vppif_reg32_read(CEC_LOGICAL_ADDR3),
vppif_reg32_read(CEC_ADDR_VALID3));
DPRINT("addr4 0x%x,valid %d\n",
vppif_reg32_read(CEC_LOGICAL_ADDR4),
vppif_reg32_read(CEC_ADDR_VALID4));
DPRINT("addr5 0x%x,valid %d\n",
vppif_reg32_read(CEC_LOGICAL_ADDR5),
vppif_reg32_read(CEC_ADDR_VALID5));
DPRINT("---------- Misc ----------\n");
DPRINT("free 3x %d,5x %d,7x %d\n", vppif_reg32_read(CEC_FREE_3X),
vppif_reg32_read(CEC_FREE_5X), vppif_reg32_read(CEC_FREE_7X));
DPRINT("reject next decode %d,comp disable %d\n",
vppif_reg32_read(CEC_REJECT_NEXT_DECODE),
vppif_reg32_read(CEC_COMP_DISABLE));
DPRINT("err handle disable %d,no ack disable %d\n",
vppif_reg32_read(CEC_ERR_HANDLE_DISABLE),
vppif_reg32_read(CEC_NO_ACK_DISABLE));
DPRINT("r1 enc ok %d,r1 dec ok %d,r1 err %d\n",
vppif_reg32_read(CEC_R1_ENCODE_OK),
vppif_reg32_read(CEC_R1_DECODE_OK),
vppif_reg32_read(CEC_R1_ERROR));
DPRINT("r1 arb fail %d,r1 no ack %d\n",
vppif_reg32_read(CEC_R1_ARB_FAIL),
vppif_reg32_read(CEC_R1_NO_ACK));
DPRINT("dec full disable %d,self rd enable %d\n",
vppif_reg32_read(CEC_DECODE_FULL_DISABLE),
vppif_reg32_read(CEC_RD_ENCODE_ENABLE));
}
