// intialization functions
void bootARM(void) {
// had to steal some code from the original SparkFun code because I don't
// understand it yet.
rprintf_devopen(putc_serial0); // Init rprintf
delay_ms(30); // wait for power to stabilize
// bring up SD / FAT *
if (! (sd_raw_init()) ) { rprintf("SD init error!\n"); }
if ( openroot() ) { rprintf("openroot error!\n"); }
// set up I/O pins *
//Setup the MP3 I/O Lines
IODIR0 |= MP3_XCS;
IODIR0 &= ~MP3_DREQ;
PINSEL1 |= 0x00000C00; // Set the MP3_DREQ Pin to be a capture pin
IODIR1 |= MP3_XDCS | MP3_GPIO0 | MP3_XRES;
//Setupt the FM Trans. Lines
IODIR1 |= FM_LA; // FM trans outputs (Leave SPI pins
IODIR1 |= FM_CS; // unconfigured for now)
//Setup the SD Card I/O Lines
IODIR0 |= SD_CS; // SD card outputs
//Setup the Accelerometer I/O Lines
IODIR0 |= (GS1 | GS2); // accelerometer outputs
// ensure ADC pins have ADC Functions selected
PINSEL0 |= (MMA_X_PINSEL | MMA_Y_PINSEL | MMA_Z_PINSEL);
IOCLR0 = (GS1 | GS2); // initialize acceleration to 1.5 G mode
//Setup the LCD I/O Lines
IODIR0 |= (LCD_RES | LCD_CS); // LCD Outputs
//Setup the LED Lines
IODIR0 |= (LED_BLU | LED_RED | LED_GRN);
ledBlueOff();
ledRedOff();
ledGrnOff();
//Setup the Buttons
IODIR1 &= (~SW_UP & ~SW_DWN & ~SW_MID); //Button Inputs
IODIR0 &= ~(1<<23); //Set the Vbus line as an input
//Setupt the Interrupts
VPBDIV = 1; // Set PCLK equal to the system clock
VICIntSelect = ~0x30; // Timer 0 AND TIMER 1 interrupt is an IRQ interrupt
VICIntEnable = 0x10; // Enable Timer 0 interrupts
// (don't start sending song data with Timer 1)
VICVectCntl0= 0x25; // Use slot 0 for timer 1 interrupt
VICVectAddr0 = (unsigned int)timer1ISR; // Set the address of ISR for slot 1
VICVectCntl1 = 0x24; // Use slot 1 for timer 0 interrupt
VICVectAddr1 = (unsigned int)timer0ISR; // Set the address of ISR for slot 1
//Configure Timer0
T0PR = 1500; // divide clock(60MHz) by 1500 for 40kHz PS
T0TCR |=0X01; // enable the clock
T0CTCR=0; // timer node
T0MCR=0x0003; // interrupt and reset timer on match
T0MR0=1000; // interrupt on 40Hz
//Configure Timer1
T1PR = 200; // divide clock by 300 for 40kHz PS
T1TCR |=0X01; // enable the clock
T1CTCR=0; // timer mode
T1CCR=0x0A00; // capture and interrupt on the
// rising edge of DREQ
//Setup the SPI Port
S0SPCCR = 64; // SCK = 1 MHz, counter > 8 and even
S0SPCR = 0x20; // Master, no interrupt enable, 8 bits
// set up MP3 decoder
vs1002Config(); // set up ARM <-> VS1002 communication
vs1002Reset(); // hardware reset
vs1002Init(); // initialization
return;
}
int main(void) {
/* Watchdog */
wdt_reset();
wdt_disable();
/* Ports */
DDRB = _BV(PINB0) | _BV(PINB2) | _BV(PINB3) | _BV(PINB5);
DDRD = _BV(PIND5) | _BV(PIND7);
PORTB = 0xff; //& (_BV(PINB0));
PORTC = 0xff;
PORTD = 0xff;// & (_BV(PIND5) | _BV(PIND6) | _BV(PIND7));
/* Power saving */
set_sleep_mode(SLEEP_MODE_IDLE);
//b = fifoCreate(255);
vs1002Reset();
DDRD |= _BV(DDD1);
UCSR0B = _BV(TXEN0) | _BV(RXEN0); // | _BV(RXCIE0);
UBRR0L = 9;
/* SPI */
SPCR = _BV(SPE) | _BV(MSTR) | _BV(SPR1) | _BV(SPR0);
//SPSR = _BV(SPI2X);
// 0x8000 + 6144 = 0x9800, 12.288MHz XTAL + clk-doubling
/* Clock */
vs1002cmd_s();
SPDR = 0x02;
loop_until_bit_is_set(SPSR, SPIF);
SPDR = 0x03;
loop_until_bit_is_set(SPSR, SPIF);
SPDR = 0x98;
loop_until_bit_is_set(SPSR, SPIF);
SPDR = 0x00;
loop_until_bit_is_set(SPSR, SPIF);
vs1002cmd_e();
/* Mode: TEST */
vs1002cmd_s();
SPDR = 0x02;
loop_until_bit_is_set(SPSR, SPIF);
SPDR = 0x00;
loop_until_bit_is_set(SPSR, SPIF);
SPDR = 0x08;
loop_until_bit_is_set(SPSR, SPIF);
SPDR = 0x20; // Test
loop_until_bit_is_set(SPSR, SPIF);
vs1002cmd_e();
/* Volume */
vs1002cmd_s();
SPDR = 0x02;
loop_until_bit_is_set(SPSR, SPIF);
SPDR = 0x0b;
loop_until_bit_is_set(SPSR, SPIF);
SPDR = 0x00;
loop_until_bit_is_set(SPSR, SPIF);
SPDR = 0x00;
loop_until_bit_is_set(SPSR, SPIF);
vs1002cmd_e();
/* Test 1.500kHz sine */
vs1002data_s();
SPDR = 0x53;
loop_until_bit_is_set(SPSR, SPIF);
SPDR = 0xef;
loop_until_bit_is_set(SPSR, SPIF);
SPDR = 0x6e;
loop_until_bit_is_set(SPSR, SPIF);
SPDR = 0x28;
loop_until_bit_is_set(SPSR, SPIF);
SPDR = 0x00;
loop_until_bit_is_set(SPSR, SPIF);
SPDR = 0x00;
loop_until_bit_is_set(SPSR, SPIF);
SPDR = 0x00;
loop_until_bit_is_set(SPSR, SPIF);
SPDR = 0x00;
loop_until_bit_is_set(SPSR, SPIF);
vs1002data_e();
uint8_t t;
for (t = 0; t < 125; t++) {
_delay_ms(2);
}
/* End test */
vs1002data_s();
SPDR = 0x45;
loop_until_bit_is_set(SPSR, SPIF);
SPDR = 0x78;
loop_until_bit_is_set(SPSR, SPIF);
SPDR = 0x69;
loop_until_bit_is_set(SPSR, SPIF);
SPDR = 0x74;
loop_until_bit_is_set(SPSR, SPIF);
SPDR = 0x00;
loop_until_bit_is_set(SPSR, SPIF);
SPDR = 0x00;
loop_until_bit_is_set(SPSR, SPIF);
SPDR = 0x00;
loop_until_bit_is_set(SPSR, SPIF);
SPDR = 0x00;
loop_until_bit_is_set(SPSR, SPIF);
vs1002data_e();
/* Mode: PLAY */
vs1002cmd_s();
SPDR = 0x02;
loop_until_bit_is_set(SPSR, SPIF);
SPDR = 0x00;
loop_until_bit_is_set(SPSR, SPIF);
SPDR = 0x08;
loop_until_bit_is_set(SPSR, SPIF);
SPDR = 0x08; // STREAM
loop_until_bit_is_set(SPSR, SPIF);
vs1002cmd_e();
uint16_t i;
uint8_t buffer[1000];
for (;;) {
uartTx('.');
for (i = 0; i < 1000; i++) {
loop_until_bit_is_set(UCSR0A, RXC0);
buffer[i] = UDR0;
}
loop_until_bit_is_set(VS1002_DREQ_PORT, VS1002_DREQ_PIN);
vs1002data_s();
for (i = 0; i < 1000; i++) {
loop_until_bit_is_set(SPSR, SPIF);
SPDR = buffer[i];
}
vs1002data_e();
}
}
