static void vx2_setup_pseudo_dma(struct vx_core *chip, int do_write)
{
/*
*/
vx_outl(chip, ICR, do_write ? ICR_TREQ : ICR_RREQ);
/*
*/
vx_outl(chip, RESET_DMA, 0);
}
/**
* vx_setup_pseudo_dma - set up the pseudo dma read/write mode.
* @do_write: 0 = read, 1 = set up for DMA write
*/
static void vx2_setup_pseudo_dma(struct vx_core *chip, int do_write)
{
/* Interrupt mode and HREQ pin enabled for host transmit data transfers
* (in case of the use of the pseudo-dma facility).
*/
vx_outl(chip, ICR, do_write ? ICR_TREQ : ICR_RREQ);
/* Reset the pseudo-dma register (in case of the use of the
* pseudo-dma facility).
*/
vx_outl(chip, RESET_DMA, 0);
}
static void vx2_reset_dsp(struct vx_core *_chip)
{
struct snd_vx222 *chip = (struct snd_vx222 *)_chip;
/* set the reset dsp bit to 0 */
vx_outl(chip, CDSP, chip->regCDSP & ~VX_CDSP_DSP_RESET_MASK);
mdelay(XX_DSP_RESET_WAIT_TIME);
chip->regCDSP |= VX_CDSP_DSP_RESET_MASK;
/* set the reset dsp bit to 1 */
vx_outl(chip, CDSP, chip->regCDSP);
}
static int vx2_test_xilinx(struct vx_core *_chip)
{
struct snd_vx222 *chip = (struct snd_vx222 *)_chip;
unsigned int data;
snd_printdd("testing xilinx...\n");
/* This test uses several write/read sequences on TEST0 and TEST1 bits
* to figure out whever or not the xilinx was correctly loaded
*/
/* We write 1 on CDSP.TEST0. We should get 0 on STATUS.TEST0. */
vx_outl(chip, CDSP, chip->regCDSP | VX_CDSP_TEST0_MASK);
vx_inl(chip, ISR);
data = vx_inl(chip, STATUS);
if ((data & VX_STATUS_VAL_TEST0_MASK) == VX_STATUS_VAL_TEST0_MASK) {
snd_printdd("bad!\n");
return -ENODEV;
}
/* We write 0 on CDSP.TEST0. We should get 1 on STATUS.TEST0. */
vx_outl(chip, CDSP, chip->regCDSP & ~VX_CDSP_TEST0_MASK);
vx_inl(chip, ISR);
data = vx_inl(chip, STATUS);
if (! (data & VX_STATUS_VAL_TEST0_MASK)) {
snd_printdd("bad! #2\n");
return -ENODEV;
}
if (_chip->type == VX_TYPE_BOARD) {
/* not implemented on VX_2_BOARDS */
/* We write 1 on CDSP.TEST1. We should get 0 on STATUS.TEST1. */
vx_outl(chip, CDSP, chip->regCDSP | VX_CDSP_TEST1_MASK);
vx_inl(chip, ISR);
data = vx_inl(chip, STATUS);
if ((data & VX_STATUS_VAL_TEST1_MASK) == VX_STATUS_VAL_TEST1_MASK) {
snd_printdd("bad! #3\n");
return -ENODEV;
}
/* We write 0 on CDSP.TEST1. We should get 1 on STATUS.TEST1. */
vx_outl(chip, CDSP, chip->regCDSP & ~VX_CDSP_TEST1_MASK);
vx_inl(chip, ISR);
data = vx_inl(chip, STATUS);
if (! (data & VX_STATUS_VAL_TEST1_MASK)) {
snd_printdd("bad! #4\n");
return -ENODEV;
}
}
snd_printdd("ok, xilinx fine.\n");
return 0;
}
static int vx2_test_xilinx(struct vx_core *_chip)
{
struct snd_vx222 *chip = (struct snd_vx222 *)_chip;
unsigned int data;
snd_printdd("testing xilinx...\n");
/*
*/
/* */
vx_outl(chip, CDSP, chip->regCDSP | VX_CDSP_TEST0_MASK);
vx_inl(chip, ISR);
data = vx_inl(chip, STATUS);
if ((data & VX_STATUS_VAL_TEST0_MASK) == VX_STATUS_VAL_TEST0_MASK) {
snd_printdd("bad!\n");
return -ENODEV;
}
/* */
vx_outl(chip, CDSP, chip->regCDSP & ~VX_CDSP_TEST0_MASK);
vx_inl(chip, ISR);
data = vx_inl(chip, STATUS);
if (! (data & VX_STATUS_VAL_TEST0_MASK)) {
snd_printdd("bad! #2\n");
return -ENODEV;
}
if (_chip->type == VX_TYPE_BOARD) {
/* */
/* */
vx_outl(chip, CDSP, chip->regCDSP | VX_CDSP_TEST1_MASK);
vx_inl(chip, ISR);
data = vx_inl(chip, STATUS);
if ((data & VX_STATUS_VAL_TEST1_MASK) == VX_STATUS_VAL_TEST1_MASK) {
snd_printdd("bad! #3\n");
return -ENODEV;
}
/* */
vx_outl(chip, CDSP, chip->regCDSP & ~VX_CDSP_TEST1_MASK);
vx_inl(chip, ISR);
data = vx_inl(chip, STATUS);
if (! (data & VX_STATUS_VAL_TEST1_MASK)) {
snd_printdd("bad! #4\n");
return -ENODEV;
}
}
snd_printdd("ok, xilinx fine.\n");
return 0;
}
/*
* vx_release_pseudo_dma - disable the pseudo-DMA mode
*/
static inline void vx2_release_pseudo_dma(struct vx_core *chip)
{
/* HREQ pin disabled. */
vx_outl(chip, ICR, 0);
}
/*
* vx_release_pseudo_dma - disable the pseudo-DMA mode
*/
inline static void vx2_release_pseudo_dma(vx_core_t *chip)
{
/* HREQ pin disabled. */
vx_outl(chip, ICR, 0);
}
static inline void vx2_release_pseudo_dma(struct vx_core *chip)
{
/* */
vx_outl(chip, ICR, 0);
}
