int i2c_probe (uchar chip) { int res = 1; /* default = fail */ if (chip == readw (&i2c_base->oa)) { return res; } /* wait until bus not busy */ wait_for_bb (); /* try to read one byte */ writew (1, &i2c_base->cnt); /* set slave address */ writew (chip, &i2c_base->sa); /* stop bit needed here */ writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, &i2c_base->con); /* enough delay for the NACK bit set */ udelay (50000); if (!(readw (&i2c_base->stat) & I2C_STAT_NACK)) { res = 0; /* success case */ flush_fifo(); writew(0xFFFF, &i2c_base->stat); } else { writew(0xFFFF, &i2c_base->stat); /* failue, clear sources*/ writew (readw (&i2c_base->con) | I2C_CON_STP, &i2c_base->con); /* finish up xfer */ udelay(20000); wait_for_bb (); } flush_fifo(); writew (0, &i2c_base->cnt); /* don't allow any more data in...we don't want it.*/ writew(0xFFFF, &i2c_base->stat); return res; }
int i2c_probe (uchar chip) { int res = 1; /* default = fail */ if (chip == inw (I2C_OA)) { return res; } /* wait until bus not busy */ wait_for_bb (); /* try to read one byte */ outw (1, I2C_CNT); /* set slave address */ outw (chip, I2C_SA); /* stop bit needed here */ outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, I2C_CON); /* enough delay for the NACK bit set */ udelay (50000); if (!(inw (I2C_STAT) & I2C_STAT_NACK)) { res = 0; /* success case */ flush_fifo(); outw(0xFFFF, I2C_STAT); } else { outw(0xFFFF, I2C_STAT); /* failue, clear sources*/ outw (inw (I2C_CON) | I2C_CON_STP, I2C_CON); /* finish up xfer */ udelay(20000); wait_for_bb (); } flush_fifo(); outw (0, I2C_CNT); /* don't allow any more data in...we don't want it.*/ outw(0xFFFF, I2C_STAT); return res; }
int i2c_probe (uchar chip) { int res = 1; if (chip == inw (I2C_OA)) { return res; } /* wait until bus not busy */ wait_for_bb (); /* try to read one byte */ outw (1, I2C_CNT); /* set slave address */ outw (chip, I2C_SA); /* stop bit needed here */ outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, I2C_CON); /* enough delay for the NACK bit set */ udelay (2000); if (!(inw (I2C_STAT) & I2C_STAT_NACK)) { res = 0; } else { outw (inw (I2C_CON) | I2C_CON_STP, I2C_CON); udelay (20); wait_for_bb (); } return res; }
int i2c_probe (uchar chip) { u16 status; int res = 1; /* default = fail */ if (chip == readw (&i2c_base->oa)) { return res; } /* wait until bus not busy */ wait_for_bb (); /* try to read one byte */ writew (1, &i2c_base->cnt); /* set slave address */ writew (chip, &i2c_base->sa); /* stop bit needed here */ writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, &i2c_base->con); while (1) { status = wait_for_pin(); if (status == 0 || status & I2C_STAT_AL) { res = 1; goto probe_exit; } if (status & I2C_STAT_NACK) { res = 1; writew(0xff, &i2c_base->stat); writew (readw (&i2c_base->con) | I2C_CON_STP, &i2c_base->con); wait_for_bb (); break; } if (status & I2C_STAT_ARDY) { writew(I2C_STAT_ARDY, &i2c_base->stat); break; } if (status & I2C_STAT_RRDY) { res = 0; #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \ defined(CONFIG_OMAP44XX) readb(&i2c_base->data); #else readw(&i2c_base->data); #endif writew(I2C_STAT_RRDY, &i2c_base->stat); } } probe_exit: flush_fifo(); writew (0, &i2c_base->cnt); /* don't allow any more data in...we don't want it.*/ writew(0xFFFF, &i2c_base->stat); return res; }
static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value) { int i2c_error = 0; u16 status; /* wait until bus not busy */ wait_for_bb (); /* one byte only */ outw (1, I2C_CNT); /* set slave address */ outw (devaddr, I2C_SA); /* no stop bit needed here */ outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, I2C_CON); status = wait_for_pin (); if (!i2c_error) { /* free bus, otherwise we can't use a combined transction */ outw (0, I2C_CON); wait_for_bb (); /* set slave address */ outw (devaddr, I2C_SA); /* read one byte from slave */ outw (1, I2C_CNT); /* need stop bit here */ outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, I2C_CON); status = wait_for_pin (); if (status & I2C_STAT_RRDY) { *value = inw (I2C_DRR); udelay (20000); } else { i2c_error = 1; } if (!i2c_error) { outw (I2C_CON_EN, I2C_CON); } } flush_fifo(); outw (0xFFFF, I2C_STAT); outw (0, I2C_CNT); return i2c_error; }
int i2c_probe (uint8_t chip) { uint16_t status; int res = 1; /* default = fail */ if (chip == readw (&i2c_base->oa)) { return res; } /* wait until bus not busy */ wait_for_bb (); /* try to write one byte */ writew (1, &i2c_base->cnt); /* set slave address */ writew (chip, &i2c_base->sa); /* stop bit needed here */ writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP, &i2c_base->con); status = wait_for_pin(); /* check for ACK (!NAK) */ if (!(status & I2C_STAT_NACK)) res = 0; /* abort transfer (force idle state) */ writew(0, &i2c_base->con); flush_fifo(); writew (0, &i2c_base->cnt); /* don't allow any more data in...we don't want it.*/ writew(0xFFFF, &i2c_base->stat); return res; }
int i2c_probe(uchar chip) { int res = 1; /* default = fail */ u32 status; if (chip == readw ((i2c_base + I2C_OA_OFS))) return res; /* wait until bus not busy */ status = wait_for_bb(); /* exiting on BUS busy */ if (status & I2C_TIMEOUT) return res; /* try to read one byte */ writew (1, (i2c_base + I2C_CNT_OFS)); /* set slave address */ writew (chip, (i2c_base + I2C_SA_OFS)); /* stop bit needed here */ writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, (i2c_base + I2C_CON_OFS)); /* enough delay for the NACK bit set */ udelay (50000); if (!(readw ((i2c_base + I2C_STAT_OFS)) & I2C_STAT_NACK)) { res = 0; /* success case */ flush_fifo(); writew(0xFFFF, (i2c_base + I2C_STAT_OFS)); } else { writew(0xFFFF, (i2c_base + I2C_STAT_OFS)); /* failue, clear sources*/ /* finish up xfer */ writew(readw((i2c_base + I2C_CON_OFS)) | I2C_CON_STP, (i2c_base + I2C_CON_OFS)); udelay(20000); wait_for_bb(); status = wait_for_bb(); /* exiting on BUS busy */ if (status & I2C_TIMEOUT) return res; } flush_fifo(); /* don't allow any more data in...we don't want it.*/ writew(0, (i2c_base + I2C_CNT_OFS)); writew(0xFFFF, (i2c_base + I2C_STAT_OFS)); return res; }
/* After we issue a transaction on the IIC bus, this function * is called. It puts this process to sleep until we get an interrupt from * from the controller telling us that the transaction we requested in complete. */ static int wait_for_pin(struct i2c_algo_iic_data *adap, short *status) { int timeout = DEF_TIMEOUT; timeout = wait_for_bb(adap); if (timeout) { DEB2(printk("Timeout waiting for host not busy\n");) return -EIO; }
static void __omap24_i2c_init(struct i2c *i2c_base, int speed, int slaveadd, int *waitdelay) { int timeout = I2C_TIMEOUT; int deblock = 1; retry: if (readw(&i2c_base->con) & I2C_CON_EN) { writew(0, &i2c_base->con); udelay(50000); } writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */ udelay(1000); writew(I2C_CON_EN, &i2c_base->con); while (!(readw(&i2c_base->syss) & I2C_SYSS_RDONE) && timeout--) { if (timeout <= 0) { puts("ERROR: Timeout in soft-reset\n"); return; } udelay(1000); } if (0 != __omap24_i2c_setspeed(i2c_base, speed, waitdelay)) { printf("ERROR: failed to setup I2C bus-speed!\n"); return; } /* own address */ writew(slaveadd, &i2c_base->oa); #if defined(CONFIG_OMAP34XX) /* * Have to enable interrupts for OMAP2/3, these IPs don't have * an 'irqstatus_raw' register and we shall have to poll 'stat' */ writew(I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie); #endif udelay(1000); flush_fifo(i2c_base); writew(0xFFFF, &i2c_base->stat); /* Handle possible failed I2C state */ if (wait_for_bb(i2c_base, *waitdelay)) if (deblock == 1) { omap24_i2c_deblock(i2c_base); deblock = 0; goto retry; } }
/* * i2c_probe: Use write access. Allows to identify addresses that are * write-only (like the config register of dual-port EEPROMs) */ static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip) { struct i2c *i2c_base = omap24_get_base(adap); u16 status; int res = 1; /* default = fail */ if (chip == readw(&i2c_base->oa)) return res; /* Wait until bus is free */ if (wait_for_bb(adap)) return res; /* No data transfer, slave addr only */ writew(chip, &i2c_base->sa); /* Stop bit needed here */ writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP, &i2c_base->con); status = wait_for_event(adap); if ((status & ~I2C_STAT_XRDY) == 0 || (status & I2C_STAT_AL)) { /* * With current high-level command implementation, notifying * the user shall flood the console with 127 messages. If * silent exit is desired upon unconfigured bus, remove the * following 'if' section: */ if (status == I2C_STAT_XRDY) printf("i2c_probe: pads on bus %d probably not configured (status=0x%x)\n", adap->hwadapnr, status); goto pr_exit; } /* Check for ACK (!NAK) */ if (!(status & I2C_STAT_NACK)) { res = 0; /* Device found */ udelay(adap->waitdelay);/* Required by AM335X in SPL */ /* Abort transfer (force idle state) */ writew(I2C_CON_MST | I2C_CON_TRX, &i2c_base->con); /* Reset */ udelay(1000); writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_TRX | I2C_CON_STP, &i2c_base->con); /* STP */ } pr_exit: flush_fifo(adap); writew(0xFFFF, &i2c_base->stat); return res; }
static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value) { int i2c_error = 0; u16 status, stat; /* wait until bus not busy */ wait_for_bb (); /* two bytes */ outw (2, I2C_CNT); /* set slave address */ outw (devaddr, I2C_SA); /* stop bit needed here */ outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP, I2C_CON); /* wait until state change */ status = wait_for_pin (); if (status & I2C_STAT_XRDY) { /* send out two bytes */ outw ((value << 8) + regoffset, I2C_DATA); /* must have enough delay to allow BB bit to go low */ udelay (50000); if (inw (I2C_STAT) & I2C_STAT_NACK) { i2c_error = 1; } } else { i2c_error = 1; } if (!i2c_error) { int eout = 200; outw (I2C_CON_EN, I2C_CON); while ((stat = inw (I2C_STAT)) || (inw (I2C_CON) & I2C_CON_MST)) { udelay (1000); /* have to read to clear intrrupt */ outw (0xFFFF, I2C_STAT); if(--eout == 0) /* better leave with error than hang */ break; } } flush_fifo(); outw (0xFFFF, I2C_STAT); outw (0, I2C_CNT); return i2c_error; }
static int pcf_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, int num) { struct i2c_algo_pcf_data *adap = i2c_adap->algo_data; struct i2c_msg *pmsg; int i; int ret=0, timeout, status; /* Check for bus busy */ timeout = wait_for_bb(adap); if (timeout) { DEB2(printk(KERN_ERR "i2c-algo-pcf.o: " "Timeout waiting for BB in pcf_xfer\n");) return -EIO; }
static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value) { int i2c_error = 0; u16 status, stat; u16 temp; /* wait until bus not busy */ wait_for_bb (); /* two bytes */ outw (2, I2C_CNT); /* set slave address */ outw (devaddr, I2C_SA); /* stop bit needed here */ outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP, I2C_CON); /* wait until state change */ status = wait_for_pin (); if (status & I2C_STAT_XRDY) { /* send out two bytes */ outw (value, I2C_DXR); /* must have enough delay to allow BB bit to go low */ udelay (50000); if (inw (I2C_STAT) & I2C_STAT_NACK) { i2c_error = 1; } } else { i2c_error = 1; } if (!i2c_error) { outw (I2C_CON_EN, I2C_CON); do { temp = inw(I2C_STAT) && I2C_STAT_SCD; } while (!temp); } flush_fifo(); outw (0xFFFF, I2C_STAT); outw (0, I2C_CNT); return i2c_error; }
static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value) { int i2c_error = 0; u16 status; /* wait until bus not busy */ wait_for_bb (); /* two bytes */ outw (2, I2C_CNT); /* set slave address */ outw (devaddr, I2C_SA); /* stop bit needed here */ outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP, I2C_CON); /* wait until state change */ status = wait_for_pin (); if (status & I2C_STAT_XRDY) { /* send out two bytes */ outw ((value << 8) + regoffset, I2C_DATA); /* must have enough delay to allow BB bit to go low */ udelay (30000); if (inw (I2C_STAT) & I2C_STAT_NACK) { i2c_error = 1; } } else { i2c_error = 1; } if (!i2c_error) { outw (I2C_CON_EN, I2C_CON); while (inw (I2C_STAT) || (inw (I2C_CON) & I2C_CON_MST)) { udelay (1000); /* have to read to clear intrrupt */ inw (I2C_IV); } } return i2c_error; }
static int pcf_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, int num) { struct i2c_algo_pcf_data *adap = i2c_adap->algo_data; struct i2c_msg *pmsg; int i; int ret=0, timeout, status; if (adap->xfer_begin) adap->xfer_begin(adap->data); /* */ timeout = wait_for_bb(adap); if (timeout) { DEB2(printk(KERN_ERR "i2c-algo-pcf.o: " "Timeout waiting for BB in pcf_xfer\n");) i = -EIO; goto out; }
int i2c_read_2_byte(u8 devaddr, u8 regoffset, u8 * value) { int err; int i2c_error = 0; u16 status; if (!value) return 1; /* wait until bus not busy */ wait_for_bb(); /* one byte only */ outw(1, I2C_CNT); /* set slave address */ outw(devaddr, I2C_SA); /* no stop bit needed here */ outw(I2C_CON_EN | ((i2c_speed == OMAP_I2C_HIGH_SPEED) ? 0x1 << 12 : 0) | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, I2C_CON); status = wait_for_pin(); if (status & I2C_STAT_XRDY) { /* Important: have to use byte access */ outb(regoffset, I2C_DATA); /* Important: wait for ARDY bit to set */ err = 2000; while (!(inw(I2C_STAT) & I2C_STAT_ARDY) && err--) ; if (err <= 0) i2c_error = 1; if (inw(I2C_STAT) & I2C_STAT_NACK) { i2c_error = 1; } } else { i2c_error = 1; } if (!i2c_error) { err = 2000; outw(I2C_CON_EN, I2C_CON); while (inw(I2C_STAT) || (inw(I2C_CON) & I2C_CON_MST)) { /* Have to clear pending interrupt to clear I2C_STAT */ outw(0xFFFF, I2C_STAT); if (!err--) { break; } } /* set slave address */ outw(devaddr, I2C_SA); /* read two bytes from slave */ outw(2, I2C_CNT); /* need stop bit here */ outw(I2C_CON_EN | ((i2c_speed == OMAP_I2C_HIGH_SPEED) ? 0x1 << 12 : 0) | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, I2C_CON); status = wait_for_pin(); if (status & I2C_STAT_RRDY) { int i =0; for (i=0; i<2; i++) { #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || defined(CONFIG_OMAP44XX) *value++ = inb(I2C_DATA); #else *value = inw(I2C_DATA); #endif /* Important: wait for ARDY bit to set */ err = 20000; while (!(inw(I2C_STAT) & I2C_STAT_ARDY) && err--); } if (err <= 0){ printf("i2c_read_byte -- I2C_STAT_ARDY error\n"); i2c_error = 1; } } else { i2c_error = 1; } if (!i2c_error) { int err = 1000; outw(I2C_CON_EN, I2C_CON); while (inw(I2C_STAT) || (inw(I2C_CON) & I2C_CON_MST)) { outw(0xFFFF, I2C_STAT); if (!err--) { break; } } } } flush_fifo(); outw(0xFFFF, I2C_STAT); outw(0, I2C_CNT); return i2c_error; }
static int i2c_multidata_write_byte(u8 devaddr, u8 regoffset, u8 *values, int len) { int eout; int i2c_error = 0; u16 status, stat; int i=0; int count=0; /* wait until bus not busy */ wait_for_bb(); //printf("I2C DEBUG: Bus not busy complete\n"); count = len + 1; /* length+1 bytes */ outw(count, I2C_CNT); //printf("I2C DEBUG: Count set to %x\n", count); /* set slave address */ outw(devaddr, I2C_SA); //printf("I2C DEBUG: Slave Address set to %x\n", devaddr); /* stop bit needed here */ outw(I2C_CON_EN | ((i2c_speed == OMAP_I2C_HIGH_SPEED) ? 0x1 << 12 : 0) | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP, I2C_CON); //printf("I2C DEBUG: Configuration set\n"); /* wait until state change */ status = wait_for_pin(); //printf("I2C DEBUG: Wait pin status change\n"); if (status & I2C_STAT_XRDY) { #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || defined(CONFIG_OMAP44XX) /* send out 1 byte */ //printf("I2C DEBUG: Transmit ready status\n"); outb(regoffset, I2C_DATA); //printf("I2C DEBUG: Register Offset set to %x\n", regoffset); outw(I2C_STAT_XRDY, I2C_STAT); //printf("I2C DEBUG: Clearing transmit ready\n"); for (i = 0; i < len; i++) { status = wait_for_pin(); //printf("I2C DEBUG: Wait pin status change\n"); if ((status & I2C_STAT_XRDY)) { //printf("I2C DEBUG: Data output iteration %x\n", i); /* send out next 1 byte */ outb(values[i], I2C_DATA); //printf("I2C DEBUG: Data output value written %x\n", values[i]); outw(I2C_STAT_XRDY, I2C_STAT); //printf("I2C DEBUG: Clearing transmit ready \n"); } else { printf("I2C error\n"); i2c_error = 1; } } //printf("I2C DEBUG: Multidata byte write transfer complete \n"); #else /* send out 2 bytes */ outw((value << 8) | regoffset, I2C_DATA); #endif /* must have enough delay to allow BB bit to go low */ eout= 20000; while (!(inw(I2C_STAT) & I2C_STAT_ARDY) && eout--) ; if (eout <= 0) printf("timed out in i2c_write_byte: I2C_STAT=%x\n", inw(I2C_STAT)); if (inw(I2C_STAT) & I2C_STAT_NACK) { i2c_error = 1; } } else { i2c_error = 1; } if (!i2c_error) { eout = 2000; outw(I2C_CON_EN, I2C_CON); while ((stat = inw(I2C_STAT)) || (inw(I2C_CON) & I2C_CON_MST)) { /* have to read to clear intrrupt */ outw(0xFFFF, I2C_STAT); if (--eout == 0) /* better leave with error than hang */ break; } } flush_fifo(); outw(0xFFFF, I2C_STAT); outw(0, I2C_CNT); return i2c_error; }
static int i2c_read_byte(u8 devaddr, u8 regoffset, u8 * value) { int i2c_error = 0; u16 status; /* wait until bus not busy */ wait_for_bb(); /* one byte only */ outw(1, I2C_CNT); /* set slave address */ outw(devaddr, I2C_SA); /* no stop bit needed here */ outw(I2C_CON_EN | ((i2c_speed == OMAP_I2C_HIGH_SPEED) ? 0x1 << 12 : 0) | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, I2C_CON); status = wait_for_pin(); if (status & I2C_STAT_XRDY) { /* Important: have to use byte access */ outb(regoffset, I2C_DATA); udelay(20000); if (inw(I2C_STAT) & I2C_STAT_NACK) { i2c_error = 1; } } else { i2c_error = 1; } if (!i2c_error) { int err = 10; while (inw(I2C_STAT) || (inw(I2C_CON) & I2C_CON_MST)) { udelay(10000); /* Have to clear pending interrupt to clear I2C_STAT */ outw(0xFFFF, I2C_STAT); if (!err--) { break; } } /* set slave address */ outw(devaddr, I2C_SA); /* read one byte from slave */ outw(1, I2C_CNT); /* need stop bit here */ outw(I2C_CON_EN | ((i2c_speed == OMAP_I2C_HIGH_SPEED) ? 0x1 << 12 : 0) | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, I2C_CON); status = wait_for_pin(); if (status & I2C_STAT_RRDY) { #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || defined(CONFIG_OMAP44XX) *value = inb(I2C_DATA); #else *value = inw(I2C_DATA); #endif udelay(20000); } else { i2c_error = 1; } if (!i2c_error) { int err = 10; outw(I2C_CON_EN, I2C_CON); while (inw(I2C_STAT) || (inw(I2C_CON) & I2C_CON_MST)) { udelay(10000); outw(0xFFFF, I2C_STAT); if (!err--) { break; } } } } flush_fifo(); outw(0xFFFF, I2C_STAT); outw(0, I2C_CNT); return i2c_error; }
static int i2c_write_byte(u8 devaddr, u8 regoffset, u8 value) { int i2c_error = 0; u16 status, stat; /* wait until bus not busy */ wait_for_bb(); /* two bytes */ outw(2, I2C_CNT); /* set slave address */ outw(devaddr, I2C_SA); /* stop bit needed here */ outw(I2C_CON_EN | ((i2c_speed == OMAP_I2C_HIGH_SPEED) ? 0x1 << 12 : 0) | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP, I2C_CON); /* wait until state change */ status = wait_for_pin(); if (status & I2C_STAT_XRDY) { #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || defined(CONFIG_OMAP44XX) /* send out 1 byte */ outb(regoffset, I2C_DATA); outw(I2C_STAT_XRDY, I2C_STAT); status = wait_for_pin(); if ((status & I2C_STAT_XRDY)) { /* send out next 1 byte */ outb(value, I2C_DATA); outw(I2C_STAT_XRDY, I2C_STAT); } else { i2c_error = 1; } #else /* send out 2 bytes */ outw((value << 8) | regoffset, I2C_DATA); #endif /* must have enough delay to allow BB bit to go low */ udelay(50000); if (inw(I2C_STAT) & I2C_STAT_NACK) { i2c_error = 1; } } else { i2c_error = 1; } if (!i2c_error) { int eout = 200; outw(I2C_CON_EN, I2C_CON); while ((stat = inw(I2C_STAT)) || (inw(I2C_CON) & I2C_CON_MST)) { udelay(1000); /* have to read to clear intrrupt */ outw(0xFFFF, I2C_STAT); if (--eout == 0) /* better leave with error than hang */ break; } } flush_fifo(); outw(0xFFFF, I2C_STAT); outw(0, I2C_CNT); return i2c_error; }
static int pcf_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, int num) { struct i2c_algo_pcf_data *adap = i2c_adap->algo_data; struct i2c_msg *pmsg; int i; int ret=0, timeout, status; if (adap->xfer_begin) adap->xfer_begin(adap->data); /* Check for bus busy */ timeout = wait_for_bb(adap); if (timeout) { // DEB2(printk(KERN_ERR "i2c-algo-pcf.o: " ; i = -EIO; goto out; } for (i = 0;ret >= 0 && i < num; i++) { pmsg = &msgs[i]; // DEB2(printk(KERN_DEBUG "i2c-algo-pcf.o: Doing %s %d bytes to 0x%02x - %d of %d messages\n", // pmsg->flags & I2C_M_RD ? "read" : "write", ; ret = pcf_doAddress(adap, pmsg); /* Send START */ if (i == 0) i2c_start(adap); /* Wait for PIN (pending interrupt NOT) */ timeout = wait_for_pin(adap, &status); if (timeout) { if (timeout == -EINTR) { /* arbitration lost */ i = -EINTR; goto out; } i2c_stop(adap); // DEB2(printk(KERN_ERR "i2c-algo-pcf.o: Timeout waiting " ; i = -EREMOTEIO; goto out; } /* Check LRB (last rcvd bit - slave ack) */ if (status & I2C_PCF_LRB) { i2c_stop(adap); ; i = -EREMOTEIO; goto out; } // DEB3(printk(KERN_DEBUG "i2c-algo-pcf.o: Msg %d, addr=0x%x, flags=0x%x, len=%d\n", ; if (pmsg->flags & I2C_M_RD) { ret = pcf_readbytes(i2c_adap, pmsg->buf, pmsg->len, (i + 1 == num)); if (ret != pmsg->len) { // DEB2(printk(KERN_DEBUG "i2c-algo-pcf.o: fail: " ; } else { ; } } else { ret = pcf_sendbytes(i2c_adap, pmsg->buf, pmsg->len, (i + 1 == num)); if (ret != pmsg->len) { // DEB2(printk(KERN_DEBUG "i2c-algo-pcf.o: fail: " ; } else { ; } } } out: if (adap->xfer_end) adap->xfer_end(adap->data); return i; }
/* * i2c_read: Function now uses a single I2C read transaction with bulk transfer * of the requested number of bytes (note that the 'i2c md' command * limits this to 16 bytes anyway). If CONFIG_I2C_REPEATED_START is * defined in the board config header, this transaction shall be with * Repeated Start (Sr) between the address and data phases; otherwise * Stop-Start (P-S) shall be used (some I2C chips do require a P-S). * The address (reg offset) may be 0, 1 or 2 bytes long. * Function now reads correctly from chips that return more than one * byte of data per addressed register (like TI temperature sensors), * or that do not need a register address at all (such as some clock * distributors). */ static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, int alen, uchar *buffer, int len) { struct i2c *i2c_base = omap24_get_base(adap); int i2c_error = 0; u16 status; if (alen < 0) { puts("I2C read: addr len < 0\n"); return 1; } if (len < 0) { puts("I2C read: data len < 0\n"); return 1; } if (buffer == NULL) { puts("I2C read: NULL pointer passed\n"); return 1; } if (alen > 2) { printf("I2C read: addr len %d not supported\n", alen); return 1; } if (addr + len > (1 << 16)) { puts("I2C read: address out of range\n"); return 1; } /* Wait until bus not busy */ if (wait_for_bb(adap)) return 1; /* Zero, one or two bytes reg address (offset) */ writew(alen, &i2c_base->cnt); /* Set slave address */ writew(chip, &i2c_base->sa); if (alen) { /* Must write reg offset first */ #ifdef CONFIG_I2C_REPEATED_START /* No stop bit, use Repeated Start (Sr) */ writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, &i2c_base->con); #else /* Stop - Start (P-S) */ writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP | I2C_CON_TRX, &i2c_base->con); #endif /* Send register offset */ while (1) { status = wait_for_event(adap); /* Try to identify bus that is not padconf'd for I2C */ if (status == I2C_STAT_XRDY) { i2c_error = 2; printf("i2c_read (addr phase): pads on bus %d probably not configured (status=0x%x)\n", adap->hwadapnr, status); goto rd_exit; } if (status == 0 || (status & I2C_STAT_NACK)) { i2c_error = 1; printf("i2c_read: error waiting for addr ACK (status=0x%x)\n", status); goto rd_exit; } if (alen) { if (status & I2C_STAT_XRDY) { alen--; /* Do we have to use byte access? */ writeb((addr >> (8 * alen)) & 0xff, &i2c_base->data); writew(I2C_STAT_XRDY, &i2c_base->stat); } } if (status & I2C_STAT_ARDY) { writew(I2C_STAT_ARDY, &i2c_base->stat); break; } } }
int generic_i2c_read(u8 devaddr, u8 *value, u8 len) { int i2c_error = 0; u16 status; u8 i = 0; /* wait until bus not busy */ wait_for_bb(); /* set slave address */ outw(devaddr, I2C_SA); /* read <len> byte from slave */ outw(len, I2C_CNT); /* need stop bit here */ outw(I2C_CON_EN | ((i2c_speed == OMAP_I2C_HIGH_SPEED) ? 0x1 << 12 : 0) | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, I2C_CON); for (i = 0; (i < len) && (!i2c_error); i++) { status = wait_for_pin(); if (status & I2C_STAT_RRDY) { #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || defined(CONFIG_OMAP44XX) value[i] = inb(I2C_DATA); #else value[i] = inw(I2C_DATA); #endif } else { i2c_error = 1; } } if (i2c_error) { printf("I2C read: I/O error\n"); } else { printf("done\n"); } if (!i2c_error) { int err = 10; outw(I2C_CON_EN, I2C_CON); while (inw(I2C_STAT) || (inw(I2C_CON) & I2C_CON_MST)) { udelay(10000); outw(0xFFFF, I2C_STAT); if (!err--) { break; } } } flush_fifo(); outw(0xFFFF, I2C_STAT); outw(0, I2C_CNT); return i2c_error; }
int generic_i2c_write(u8 devaddr, u8 *value, u8 len) { int eout = 500; int i2c_error = 0; u16 status, stat; u8 i = 0; /* wait until bus not busy */ wait_for_bb(); /* <len> bytes */ outw(len, I2C_CNT); /* set slave address */ outw(devaddr, I2C_SA); /* stop bit needed here */ outw(I2C_CON_EN | ((i2c_speed == OMAP_I2C_HIGH_SPEED) ? 0x1 << 12 : 0) | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP, I2C_CON); for (i = 0; (i < len) && (!i2c_error); i++) { /* wait until state change */ status = wait_for_pin(); if (status & I2C_STAT_XRDY) { #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || defined(CONFIG_OMAP44XX) /* send out 1 byte */ outb(value[i], I2C_DATA); #endif } else { i2c_error = 1; } } if (i2c_error) { printf("I2C read: I/O error\n"); } else { printf("done\n"); } /* must have enough delay to allow BB bit to go low */ while (!(inw(I2C_STAT) & I2C_STAT_ARDY) && eout--) udelay(100); if (inw(I2C_STAT) & I2C_STAT_NACK) { i2c_error = 1; } if (!i2c_error) { eout = 200; outw(I2C_CON_EN, I2C_CON); while ((stat = inw(I2C_STAT)) || (inw(I2C_CON) & I2C_CON_MST)) { udelay(1000); /* have to read to clear intrrupt */ outw(0xFFFF, I2C_STAT); if (--eout == 0) /* better leave with error than hang */ break; } } flush_fifo(); outw(0xFFFF, I2C_STAT); outw(0, I2C_CNT); return i2c_error; }
static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value) { int i2c_error = 0; u16 status; /* wait until bus not busy */ wait_for_bb (); /* one byte only */ outw (1, I2C_CNT); /* set slave address */ outw (devaddr, I2C_SA); /* no stop bit needed here */ outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, I2C_CON); status = wait_for_pin (); if (status & I2C_STAT_XRDY) { /* Important: have to use byte access */ *(volatile u8 *) (I2C_DATA) = regoffset; udelay (20000); if (inw (I2C_STAT) & I2C_STAT_NACK) { i2c_error = 1; } } else { i2c_error = 1; } if (!i2c_error) { /* free bus, otherwise we can't use a combined transction */ outw (0, I2C_CON); while (inw (I2C_STAT) || (inw (I2C_CON) & I2C_CON_MST)) { udelay (10000); /* Have to clear pending interrupt to clear I2C_STAT */ inw (I2C_IV); } wait_for_bb (); /* set slave address */ outw (devaddr, I2C_SA); /* read one byte from slave */ outw (1, I2C_CNT); /* need stop bit here */ outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, I2C_CON); status = wait_for_pin (); if (status & I2C_STAT_RRDY) { *value = inw (I2C_DATA); udelay (20000); } else { i2c_error = 1; } if (!i2c_error) { outw (I2C_CON_EN, I2C_CON); while (inw (I2C_STAT) || (inw (I2C_CON) & I2C_CON_MST)) { udelay (10000); inw (I2C_IV); } } } return i2c_error; }
/* * i2c_read: Function now uses a single I2C read transaction with bulk transfer * of the requested number of bytes (note that the 'i2c md' command * limits this to 16 bytes anyway). If CONFIG_I2C_REPEATED_START is * defined in the board config header, this transaction shall be with * Repeated Start (Sr) between the address and data phases; otherwise * Stop-Start (P-S) shall be used (some I2C chips do require a P-S). * The address (reg offset) may be 0, 1 or 2 bytes long. * Function now reads correctly from chips that return more than one * byte of data per addressed register (like TI temperature sensors), * or that do not need a register address at all (such as some clock * distributors). */ static int __omap24_i2c_read(struct i2c *i2c_base, int waitdelay, uchar chip, uint addr, int alen, uchar *buffer, int len) { int i2c_error = 0; u16 status; if (alen < 0) { puts("I2C read: addr len < 0\n"); return 1; } if (len < 0) { puts("I2C read: data len < 0\n"); return 1; } if (buffer == NULL) { puts("I2C read: NULL pointer passed\n"); return 1; } if (alen > 2) { printf("I2C read: addr len %d not supported\n", alen); return 1; } if (addr + len > (1 << 16)) { puts("I2C read: address out of range\n"); return 1; } #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW /* * EEPROM chips that implement "address overflow" are ones * like Catalyst 24WC04/08/16 which has 9/10/11 bits of * address and the extra bits end up in the "chip address" * bit slots. This makes a 24WC08 (1Kbyte) chip look like * four 256 byte chips. * * Note that we consider the length of the address field to * still be one byte because the extra address bits are * hidden in the chip address. */ if (alen > 0) chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); #endif /* Wait until bus not busy */ if (wait_for_bb(i2c_base, waitdelay)) return 1; /* Zero, one or two bytes reg address (offset) */ writew(alen, &i2c_base->cnt); /* Set slave address */ writew(chip, &i2c_base->sa); if (alen) { /* Must write reg offset first */ #ifdef CONFIG_I2C_REPEATED_START /* No stop bit, use Repeated Start (Sr) */ writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, &i2c_base->con); #else /* Stop - Start (P-S) */ writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP | I2C_CON_TRX, &i2c_base->con); #endif /* Send register offset */ while (1) { status = wait_for_event(i2c_base, waitdelay); /* Try to identify bus that is not padconf'd for I2C */ if (status == I2C_STAT_XRDY) { i2c_error = 2; printf("i2c_read (addr phase): pads on bus probably not configured (status=0x%x)\n", status); goto rd_exit; } if (status == 0 || (status & I2C_STAT_NACK)) { i2c_error = 1; printf("i2c_read: error waiting for addr ACK (status=0x%x)\n", status); goto rd_exit; } if (alen) { if (status & I2C_STAT_XRDY) { alen--; /* Do we have to use byte access? */ writeb((addr >> (8 * alen)) & 0xff, &i2c_base->data); writew(I2C_STAT_XRDY, &i2c_base->stat); } } if (status & I2C_STAT_ARDY) { writew(I2C_STAT_ARDY, &i2c_base->stat); break; } } }
int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) { int i2c_error = 0, i; u32 status; if ((alen > 2) || (alen < 0)) { return 1; } if (addr + len > 0xFFFF) { return 1; } /* wait until bus not busy */ status = wait_for_bb(); /* exiting on BUS busy */ if (status & I2C_TIMEOUT) return 1; /* one byte only */ writew((alen & 0xFF), (i2c_base + I2C_CNT_OFS)); /* set slave address */ writew(chip, (i2c_base + I2C_SA_OFS)); /* Clear the Tx & Rx FIFOs */ writew((readw((i2c_base + I2C_BUF_OFS)) | I2C_RXFIFO_CLEAR | I2C_TXFIFO_CLEAR), (i2c_base + I2C_BUF_OFS)); /* no stop bit needed here */ writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_TRX | I2C_CON_STT, (i2c_base + I2C_CON_OFS)); /* waiting for Transmit ready condition */ status = wait_for_status_mask(I2C_STAT_XRDY | I2C_STAT_NACK); if (status & (I2C_STAT_NACK | I2C_TIMEOUT)) i2c_error = 1; if (!i2c_error) { if (status & I2C_STAT_XRDY) { switch (alen) { case 2: /* Send address MSByte */ #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)\ || defined(CONFIG_TI81XX) writew(((addr >> 8) & 0xFF), (i2c_base + I2C_DATA_OFS)); /* Clearing XRDY event */ writew((status & I2C_STAT_XRDY), (i2c_base + I2C_STAT_OFS)); /*waiting for Transmit ready * condition */ status = wait_for_status_mask(I2C_STAT_XRDY | I2C_STAT_NACK); if (status & (I2C_STAT_NACK | I2C_TIMEOUT)) { i2c_error = 1; break; } #else #endif case 1: #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)\ || defined(CONFIG_TI81XX) /* Send address LSByte */ writew((addr & 0xFF), (i2c_base + I2C_DATA_OFS)); #else /* Send address Short word */ writew((addr & 0xFFFF), (i2c_base + I2C_DATA_OFS)); #endif /* Clearing XRDY event */ writew((status & I2C_STAT_XRDY), (i2c_base + I2C_STAT_OFS)); /*waiting for Transmit ready * condition */ status = wait_for_status_mask(I2C_STAT_ARDY | I2C_STAT_NACK); if (status & (I2C_STAT_NACK | I2C_TIMEOUT)) { i2c_error = 1; break; } } } else i2c_error = 1; }
static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value) { int i2c_error = 0; u16 status, stat; /* wait until bus not busy */ wait_for_bb (); /* two bytes */ writew (2, &i2c_base->cnt); /* set slave address */ writew (devaddr, &i2c_base->sa); /* stop bit needed here */ writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP, &i2c_base->con); /* wait until state change */ status = wait_for_pin (); if (status & I2C_STAT_XRDY) { #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \ defined(CONFIG_OMAP44XX) /* send out 1 byte */ writeb (regoffset, &i2c_base->data); writew (I2C_STAT_XRDY, &i2c_base->stat); status = wait_for_pin (); if ((status & I2C_STAT_XRDY)) { /* send out next 1 byte */ writeb (value, &i2c_base->data); writew (I2C_STAT_XRDY, &i2c_base->stat); } else { i2c_error = 1; } #else /* send out two bytes */ writew ((value << 8) + regoffset, &i2c_base->data); #endif /* must have enough delay to allow BB bit to go low */ udelay (50000); if (readw (&i2c_base->stat) & I2C_STAT_NACK) { i2c_error = 1; } } else { i2c_error = 1; } if (!i2c_error) { int eout = 200; writew (I2C_CON_EN, &i2c_base->con); while ((stat = readw (&i2c_base->stat)) || (readw (&i2c_base->con) & I2C_CON_MST)) { udelay (1000); /* have to read to clear intrrupt */ writew (0xFFFF, &i2c_base->stat); if(--eout == 0) /* better leave with error than hang */ break; } } flush_fifo(); writew (0xFFFF, &i2c_base->stat); writew (0, &i2c_base->cnt); return i2c_error; }
s32 normal_i2c_read_word(u8 devaddr, u8 regoffset, u8 *value) { int error = 0; u16 status; /* wait until bus not busy */ error = wait_for_bb(); if(error) return error; /* set slave address */ I2C2_SA = devaddr; I2C2_CNT = 1; /* set slave address */ I2C2_BUF |= (1<<6 | 1<<14); /* no stop bit needed here */ I2C2_CON = 0x8603; status = wait_for_pin(); if (status & 0x10 /*I2C_STAT_XRDY*/) { /* Important: have to use byte access */ if(normal_i2c_wait_for_xudf ()) return -1; I2C2_DATA = regoffset; mdelay(2); I2C2_DATA; if ( I2C2_STAT & 0x02){ error = 1; } } else { error = 1; } if (!error) { int err = 10000; /* free bus, otherwise we can't use a combined transction */ while ((I2C2_STAT) || (I2C2_CON & 0x400)) { udelay(10); /* Have to clear pending interrupt to clear I2C_STAT */ I2C2_STAT = 0xffff; if (!err--) { break; } } error = wait_for_bb(); if(error) return error; /* set slave address */ I2C2_SA = devaddr; /* read one byte from slave */ I2C2_CNT = 3; /* need stop bit here */ I2C2_CON = 0x8403; status = wait_for_pin(); if (status & 0x08/*I2C_STAT_RRDY*/) { value[0] = I2C2_DATA; value[1] = I2C2_DATA; //mdelay(2); udelay(300); } else { error = 1; } if (!error) { int err = 10000; I2C2_CON = 0x8000; while ( I2C2_STAT || (I2C2_CON & 0x400)){ udelay(10); I2C2_STAT = 0xffff; if (!err--) { break; } } } } flush_fifo(); I2C2_STAT = 0xffff; I2C2_CNT = 0; return error; }
static int i2c_read_byte (uint8_t devaddr, uint8_t regoffset, uint8_t * value) { int i2c_error = 0; uint16_t status; /* wait until bus not busy */ wait_for_bb (); /* one byte only */ writew (1, &i2c_base->cnt); /* set slave address */ writew (devaddr, &i2c_base->sa); /* no stop bit needed here */ writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, &i2c_base->con); /* send register offset */ while (1) { status = wait_for_pin(); if (status == 0 || status & I2C_STAT_NACK) { i2c_error = 1; goto read_exit; } if (status & I2C_STAT_XRDY) { /* Important: have to use byte access */ writeb(regoffset, &i2c_base->data); writew(I2C_STAT_XRDY, &i2c_base->stat); } if (status & I2C_STAT_ARDY) { writew(I2C_STAT_ARDY, &i2c_base->stat); break; } } /* set slave address */ writew(devaddr, &i2c_base->sa); /* read one byte from slave */ writew(1, &i2c_base->cnt); /* need stop bit here */ writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, &i2c_base->con); /* receive data */ while (1) { status = wait_for_pin(); if (status == 0 || status & I2C_STAT_NACK) { i2c_error = 1; goto read_exit; } if (status & I2C_STAT_RRDY) { #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \ defined(CONFIG_OMAP44XX) *value = readb(&i2c_base->data); #else *value = readw(&i2c_base->data); #endif writew(I2C_STAT_RRDY, &i2c_base->stat); } if (status & I2C_STAT_ARDY) { writew(I2C_STAT_ARDY, &i2c_base->stat); break; } } read_exit: flush_fifo(); writew (0xFFFF, &i2c_base->stat); writew (0, &i2c_base->cnt); return i2c_error; }
static int i2c_write_byte (uint8_t devaddr, uint8_t regoffset, uint8_t value) { int i2c_error = 0; uint16_t status; /* wait until bus not busy */ wait_for_bb (); /* two bytes */ writew (2, &i2c_base->cnt); /* set slave address */ writew (devaddr, &i2c_base->sa); /* stop bit needed here */ writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP, &i2c_base->con); while (1) { status = wait_for_pin(); if (status == 0 || status & I2C_STAT_NACK) { i2c_error = 1; goto write_exit; } if (status & I2C_STAT_XRDY) { #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \ defined(CONFIG_OMAP44XX) /* send register offset */ writeb(regoffset, &i2c_base->data); writew(I2C_STAT_XRDY, &i2c_base->stat); while (1) { status = wait_for_pin(); if (status == 0 || status & I2C_STAT_NACK) { i2c_error = 1; goto write_exit; } if (status & I2C_STAT_XRDY) { /* send data */ writeb(value, &i2c_base->data); writew(I2C_STAT_XRDY, &i2c_base->stat); } if (status & I2C_STAT_ARDY) { writew(I2C_STAT_ARDY, &i2c_base->stat); break; } } break; #else /* send out two bytes */ writew((value << 8) + regoffset, &i2c_base->data); writew(I2C_STAT_XRDY, &i2c_base->stat); #endif } if (status & I2C_STAT_ARDY) { writew(I2C_STAT_ARDY, &i2c_base->stat); break; } } wait_for_bb(); status = readw(&i2c_base->stat); if (status & I2C_STAT_NACK) i2c_error = 1; write_exit: flush_fifo(); writew (0xFFFF, &i2c_base->stat); writew (0, &i2c_base->cnt); return i2c_error; }