static WRITE8_HANDLER ( exidy_wd179x_w )
{
switch (offset & 0x03)
{
case 0:
wd179x_command_w(offset, data);
return;
case 1:
wd179x_track_w(offset, data);
return;
case 2:
wd179x_sector_w(offset, data);
return;
case 3:
wd179x_data_w(offset, data);
return;
default:
break;
}
}
static WRITE8_HANDLER( coupe_port_w )
{
if (offset==SSND_ADDR) // Set sound address
{
SOUND_ADDR=data&0x1F; // 32 registers max
saa1099_control_port_0_w(0, SOUND_ADDR);
return;
}
switch (offset & 0xFF)
{
case DSK1_PORT+0: // This covers the total range of ports for 1 floppy controller
case DSK1_PORT+4:
wd179x_set_side((offset >> 2) & 1);
wd179x_command_w(0, data);
break;
case DSK1_PORT+1:
case DSK1_PORT+5:
/* Track byte requested on address line */
wd179x_set_side((offset >> 2) & 1);
wd179x_track_w(0, data);
break;
case DSK1_PORT+2:
case DSK1_PORT+6:
/* Sector byte requested on address line */
wd179x_set_side((offset >> 2) & 1);
wd179x_sector_w(0, data);
break;
case DSK1_PORT+3:
case DSK1_PORT+7:
/* Data byte requested on address line */
wd179x_set_side((offset >> 2) & 1);
wd179x_data_w(0, data);
break;
case CLUT_PORT:
CLUT[(offset >> 8)&0x0F]=data&0x7F; // set CLUT data
break;
case LINE_PORT:
LINE_INT=data; // Line to generate interrupt on
break;
case LMPR_PORT:
LMPR=data;
coupe_update_memory();
break;
case HMPR_PORT:
HMPR=data;
coupe_update_memory();
break;
case VMPR_PORT:
VMPR=data;
coupe_update_memory();
break;
case BORD_PORT:
/* DAC output state */
speaker_level_w(0,(data>>4) & 0x01);
break;
case SSND_DATA:
saa1099_write_port_0_w(0, data);
SOUND_REG[SOUND_ADDR] = data;
break;
default:
logerror("Write Unsupported Port: %04x,%02x\n", offset,data);
break;
}
}