void __dead2 sq_system_off(void)
{
volatile uint32_t *gpio = (uint32_t *)PLAT_SQ_GPIO_BASE;
/* set PD[9] high to power off the system */
gpio[5] |= 0x2; /* set output */
gpio[1] |= 0x2; /* set high */
dmbst();
generic_delay_timer_init();
mdelay(1);
while (1) {
gpio[1] &= ~0x2; /* set low */
dmbst();
mdelay(1);
gpio[1] |= 0x2; /* set high */
dmbst();
mdelay(100);
}
wfi();
ERROR("SQ System Off: operation not handled.\n");
panic();
}
void __dead2 css_scp_system_off(int state)
{
int ret;
/*
* Disable GIC CPU interface to prevent pending interrupt from waking
* up the AP from WFI.
*/
plat_arm_gic_cpuif_disable();
/*
* Issue SCMI command. First issue a graceful
* request and if that fails force the request.
*/
ret = scmi_sys_pwr_state_set(scmi_handle,
SCMI_SYS_PWR_FORCEFUL_REQ,
state);
if (ret != SCMI_E_SUCCESS) {
ERROR("SCMI system power state set 0x%x returns unexpected 0x%x\n",
state, ret);
panic();
}
wfi();
ERROR("CSS set power state: operation not handled.\n");
panic();
}
void __dead2 imx_system_reset(void)
{
sc_pm_reset(ipc_handle, SC_PM_RESET_TYPE_BOARD);
wfi();
ERROR("system reset failed.\n");
panic();
}
/*
* FVP error handler
*/
void plat_error_handler(int err)
{
int ret;
switch (err) {
case -ENOENT:
case -EAUTH:
/* Image load or authentication error. Erase the ToC */
INFO("Erasing FIP ToC from flash...\n");
nor_unlock(PLAT_ARM_FIP_BASE);
ret = nor_word_program(PLAT_ARM_FIP_BASE, 0);
if (ret) {
ERROR("Cannot erase ToC\n");
} else {
INFO("Done\n");
}
break;
default:
/* Unexpected error */
break;
}
/* Loop until the watchdog resets the system */
for (;;)
wfi();
}
void zynqmp_cpu_standby(plat_local_state_t cpu_state)
{
VERBOSE("%s: cpu_state: 0x%x\n", __func__, cpu_state);
dsb();
wfi();
}
void __dead2 imx_system_off(void)
{
sc_pm_set_sys_power_mode(ipc_handle, SC_PM_PW_MODE_OFF);
wfi();
ERROR("power off failed.\n");
panic();
}
static int rk_lpmode_enter(unsigned long arg)
{
//RKPM_DDR_PFUN(slp_setting(rkpm_jdg_sram_ctrbits),slp_setting);
RKPM_DDR_FUN(slp_setting);
local_flush_tlb_all();
flush_cache_all();
outer_flush_all();
outer_disable();
cpu_proc_fin();
//outer_inv_all();// ???
// l2x0_inv_all_pm(); //rk319x is not need
flush_cache_all();
rkpm_ddr_printch('d');
//rkpm_udelay(3*10);
dsb();
wfi();
rkpm_ddr_printch('D');
return 0;
}
/*
* rkpm enter
* module_pm_conf: callback function that control such as backlight/lcd on or off
*/
void rk_pm_enter(v_pm_cb_f module_pm_conf)
{
/* disable exceptions */
disable_interrupts();
if (module_pm_conf != NULL) {
module_pm_conf(0);
}
/* pll enter slow mode */
rkclk_pll_mode(CPLL_ID, RKCLK_PLL_MODE_SLOW);
rkclk_pll_mode(GPLL_ID, RKCLK_PLL_MODE_SLOW);
rkclk_pll_mode(APLL_ID, RKCLK_PLL_MODE_SLOW);
/* cpu enter wfi mode */
wfi();
/* pll enter nornal mode */
rkclk_pll_mode(APLL_ID, RKCLK_PLL_MODE_NORMAL);
rkclk_pll_mode(GPLL_ID, RKCLK_PLL_MODE_NORMAL);
rkclk_pll_mode(CPLL_ID, RKCLK_PLL_MODE_NORMAL);
if (module_pm_conf != NULL) {
module_pm_conf(1);
}
/* enable exceptions */
enable_interrupts();
}
static void __dead2 hikey_system_off(void)
{
NOTICE("%s: off system\n", __func__);
/* Pull down GPIO_0_0 to trigger PMIC shutdown */
mmio_write_32(0xF8001810, 0x2); /* Pinmux */
mmio_write_8(0xF8011400, 1); /* Pin direction */
mmio_write_8(0xF8011004, 0); /* Pin output value */
/* Wait for 2s to power off system by PMIC */
sp804_timer_init(SP804_TIMER0_BASE, 10, 192);
mdelay(2000);
/*
* PMIC shutdown depends on two conditions: GPIO_0_0 (PWR_HOLD) low,
* and VBUS_DET < 3.6V. For HiKey, VBUS_DET is connected to VDD_4V2
* through Jumper 1-2. So, to complete shutdown, user needs to manually
* remove Jumper 1-2.
*/
NOTICE("+------------------------------------------+\n");
NOTICE("| IMPORTANT: Remove Jumper 1-2 to shutdown |\n");
NOTICE("| DANGER: SoC is still burning. DANGER! |\n");
NOTICE("| Board will be reboot to avoid overheat |\n");
NOTICE("+------------------------------------------+\n");
/* Send the system reset request */
mmio_write_32(AO_SC_SYS_STAT0, 0x48698284);
wfi();
panic();
}
/*******************************************************************************
* Handler called when an affinity instance is about to enter standby.
******************************************************************************/
void tegra_cpu_standby(plat_local_state_t cpu_state)
{
/*
* Enter standby state
* dsb is good practice before using wfi to enter low power states
*/
dsb();
wfi();
}
static void __dead2 plat_system_reset(void)
{
/* Write the System Configuration Control Register */
mmio_write_32(VE_SYSREGS_BASE + V2M_SYS_CFGCTRL,
CFGCTRL_START | CFGCTRL_RW | CFGCTRL_FUNC(FUNC_REBOOT));
wfi();
ERROR("FVP System Reset: operation not handled.\n");
panic();
}
static void __dead2 sunxi_pwr_down_wfi(const psci_power_state_t *target_state)
{
u_register_t mpidr = read_mpidr();
sunxi_cpu_off(MPIDR_AFFLVL1_VAL(mpidr), MPIDR_AFFLVL0_VAL(mpidr));
while (1)
wfi();
}
void stop_cpu(void)
{
local_irq_disable();
cpu_is_dead = 1;
/* Make sure the write happens before we sleep forever */
dsb(sy);
isb();
while ( 1 )
wfi();
}
static void __dead2 poplar_system_reset(void)
{
mmio_write_32((uintptr_t)(HISI_WDG0_BASE + 0xc00), 0x1ACCE551);
mmio_write_32((uintptr_t)(HISI_WDG0_BASE + 0x0), 0x00000100);
mmio_write_32((uintptr_t)(HISI_WDG0_BASE + 0x8), 0x00000003);
wfi();
ERROR("Poplar System Reset: operation not handled.\n");
panic();
}
static void __dead2 hikey_system_reset(void)
{
/* Send the system reset request */
mmio_write_32(AO_SC_SYS_STAT0, 0x48698284);
isb();
dsb();
wfi();
panic();
}
static void __dead2 zynqmp_system_reset(void)
{
/* disable coherency */
plat_arm_interconnect_exit_coherency();
/* Send the system reset request to the PMU */
pm_system_shutdown(1);
while (1)
wfi();
}
/*******************************************************************************
* Platform handler called when a CPU is about to enter standby.
******************************************************************************/
static void rpi3_cpu_standby(plat_local_state_t cpu_state)
{
assert(cpu_state == PLAT_LOCAL_STATE_RET);
/*
* Enter standby state.
* dsb is good practice before using wfi to enter low power states
*/
dsb();
wfi();
}
static void __dead2 zynqmp_system_reset(void)
{
/* disable coherency */
plat_arm_interconnect_exit_coherency();
/* Send the system reset request to the PMU */
pm_system_shutdown(PMF_SHUTDOWN_TYPE_RESET,
pm_get_shutdown_scope());
while (1)
wfi();
}
static void __noreturn stm32_pm_cpu_power_down_wfi(void)
{
dcache_op_level1(DCACHE_OP_CLEAN);
io_write32(stm32_rcc_base() + RCC_MP_GRSTCSETR,
RCC_MP_GRSTCSETR_MPUP1RST);
dsb();
isb();
wfi();
panic();
}
__dead2 void tegra_soc_prepare_system_off(void)
{
mce_cstate_info_t cstate_info = { 0 };
uint32_t val;
if (tegra186_system_powerdn_state == TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF) {
/* power off the entire system */
mce_enter_ccplex_state(tegra186_system_powerdn_state);
} else if (tegra186_system_powerdn_state == TEGRA_ARI_SYSTEM_SC8) {
/* Prepare for quasi power down */
cstate_info.cluster = TEGRA_ARI_CLUSTER_CC7;
cstate_info.system = TEGRA_ARI_SYSTEM_SC8;
cstate_info.system_state_force = 1;
cstate_info.update_wake_mask = 1;
mce_update_cstate_info(&cstate_info);
/* loop until other CPUs power down */
do {
val = mce_command_handler(MCE_CMD_IS_SC7_ALLOWED,
TEGRA_ARI_CORE_C7,
MCE_CORE_SLEEP_TIME_INFINITE,
0);
} while (val == 0);
/* Enter quasi power down state */
(void)mce_command_handler(MCE_CMD_ENTER_CSTATE,
TEGRA_ARI_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0);
/* disable GICC */
tegra_gic_cpuif_deactivate();
/* power down core */
prepare_cpu_pwr_dwn();
/* flush L1/L2 data caches */
dcsw_op_all(DCCISW);
} else {
ERROR("%s: unsupported power down state (%d)\n", __func__,
tegra186_system_powerdn_state);
}
wfi();
/* wait for the system to power down */
for (;;) {
;
}
}
static void __dead2 sunxi_system_reset(void)
{
/* Reset the whole system when the watchdog times out */
mmio_write_32(SUNXI_WDOG0_CFG_REG, 1);
/* Enable the watchdog with the shortest timeout (0.5 seconds) */
mmio_write_32(SUNXI_WDOG0_MODE_REG, (0 << 4) | 1);
/* Wait for twice the watchdog timeout before panicking */
mdelay(1000);
ERROR("PSCI: System reset failed\n");
wfi();
panic();
}
/*******************************************************************************
* On Juno clear SYS_NVFLAGS and wait for watchdog reset.
******************************************************************************/
__dead2 void bl1_plat_fwu_done(void *client_cookie, void *reserved)
{
unsigned int *nv_flags_clr = (unsigned int *)
(V2M_SYSREGS_BASE + V2M_SYS_NVFLAGSCLR);
unsigned int *nv_flags_ptr = (unsigned int *)
(V2M_SYSREGS_BASE + V2M_SYS_NVFLAGS);
/* Clear the NV flags register. */
*nv_flags_clr = *nv_flags_ptr;
while (1)
wfi();
}
void __dead2 sunxi_power_down(void)
{
switch (pmic) {
case GENERIC_H5:
/* Turn off as many peripherals and clocks as we can. */
sunxi_turn_off_soc(SUNXI_SOC_H5);
/* Turn off the pin controller now. */
mmio_write_32(SUNXI_CCU_BASE + 0x68, 0);
break;
case GENERIC_A64:
/* Turn off as many peripherals and clocks as we can. */
sunxi_turn_off_soc(SUNXI_SOC_A64);
/* Turn off the pin controller now. */
mmio_write_32(SUNXI_CCU_BASE + 0x68, 0);
break;
case REF_DESIGN_H5:
sunxi_turn_off_soc(SUNXI_SOC_H5);
/*
* Switch PL pins to power off the board:
* - PL5 (VCC_IO) -> high
* - PL8 (PWR-STB = CPU power supply) -> low
* - PL9 (PWR-DRAM) ->low
* - PL10 (power LED) -> low
* Note: Clearing PL8 will reset the board, so keep it up.
*/
sunxi_set_gpio_out('L', 5, 1);
sunxi_set_gpio_out('L', 9, 0);
sunxi_set_gpio_out('L', 10, 0);
/* Turn off pin controller now. */
mmio_write_32(SUNXI_CCU_BASE + 0x68, 0);
break;
case AXP803_RSB:
/* (Re-)init RSB in case the rich OS has disabled it. */
sunxi_init_platform_r_twi(SUNXI_SOC_A64, true);
rsb_init();
/* Set "power disable control" bit */
axp_setbits(0x32, BIT(7));
break;
default:
break;
}
udelay(1000);
ERROR("PSCI: Cannot turn off system, halting.\n");
wfi();
panic();
}
static void init_other_hart()
{
// wait until virtual memory is enabled
while (root_page_table == NULL)
asm volatile ("" ::: "memory");
mb();
write_csr(sptbr, root_page_table);
// then make sure we're in bounds
if (HLS()->hart_id >= num_harts) {
while (1)
wfi();
}
boot_other_hart();
}
void __dead2 sq_system_reset(void)
{
#if SQ_USE_SCMI_DRIVER
sq_scmi_sys_reboot();
#else
uint32_t response;
/* Send the system reset request to the SCP */
response = scpi_sys_power_state(scpi_system_reboot);
if (response != SCP_OK) {
ERROR("SQ System Reset: SCP error %u.\n", response);
panic();
}
wfi();
ERROR("SQ System Reset: operation not handled.\n");
panic();
#endif
}
void idle_loop(void)
{
for ( ; ; )
{
if ( cpu_is_offline(smp_processor_id()) )
stop_cpu();
local_irq_disable();
if ( cpu_is_haltable(smp_processor_id()) )
{
dsb(sy);
wfi();
}
local_irq_enable();
do_tasklet();
do_softirq();
}
}
/*******************************************************************************
* RockChip handler called when a CPU is about to enter standby.
******************************************************************************/
void rockchip_cpu_standby(plat_local_state_t cpu_state)
{
unsigned int scr;
assert(cpu_state == PLAT_MAX_RET_STATE);
scr = read_scr_el3();
/* Enable PhysicalIRQ bit for NS world to wake the CPU */
write_scr_el3(scr | SCR_IRQ_BIT);
isb();
dsb();
wfi();
/*
* Restore SCR to the original value, synchronisation of scr_el3 is
* done by eret while el3_exit to save some execution cycles.
*/
write_scr_el3(scr);
}
int main(void)
{
setupGPIO(); //Setup general purpose input/output
setupDAC(); //Setup digital to analog converter
setupTimer(); //Setup timer
/*page 140 manual. Used to prescale the clock.
*Only used for testing purposes*/
//*CMU_HFPERCLKDIV = (1<<8) | (4 << 0);
//Setup ability to deep sleep
*SETUP_SCR |= 6;
while(1)
{
wfi(); //call wait for inerrupt
}
return 0;
}
static void __dead2 rpi3_watchdog_reset(void)
{
uint32_t rstc;
console_flush();
dsbsy();
isb();
mmio_write_32(RPI3_PM_BASE + RPI3_PM_WDOG_OFFSET,
RPI3_PM_PASSWORD | RESET_TIMEOUT);
rstc = mmio_read_32(RPI3_PM_BASE + RPI3_PM_RSTC_OFFSET);
rstc &= ~RPI3_PM_RSTC_WRCFG_MASK;
rstc |= RPI3_PM_PASSWORD | RPI3_PM_RSTC_WRCFG_FULL_RESET;
mmio_write_32(RPI3_PM_BASE + RPI3_PM_RSTC_OFFSET, rstc);
for (;;) {
wfi();
}
}
static void __dead2 zynqmp_nopmu_system_reset(void)
{
/*
* This currently triggers a system reset. I.e. the whole
* system will be reset! Including RPUs, PMU, PL, etc.
*/
/* disable coherency */
plat_arm_interconnect_exit_coherency();
/* bypass RPLL (needed on 1.0 silicon) */
uint32_t reg = mmio_read_32(CRL_APB_RPLL_CTRL);
reg |= CRL_APB_RPLL_CTRL_BYPASS;
mmio_write_32(CRL_APB_RPLL_CTRL, reg);
/* trigger system reset */
mmio_write_32(CRL_APB_RESET_CTRL, CRL_APB_RESET_CTRL_SOFT_RESET);
while (1)
wfi();
}