void GLCD_Clear (unsigned short color) { unsigned long i; GLCD_WindowMax(); wr_reg(0x20, 0); wr_reg(0x21, 0); LCD_CS(0) wr_cmd(0x22); wr_dat_start(); for(i = 0; i < ((unsigned long)WIDTH * (unsigned long)HEIGHT); i++) wr_dat_only(color); wr_dat_stop(); }
void GLCD_SetCursor(unsigned short x, unsigned short y) { #ifdef ILI9341 ili9341_set_window (x, x, y, y); #else wr_reg(0x20,x); wr_reg(0x21,y); #endif }
void test_gpio( void ) { wr_reg( 0x0304, 0x0123 ); // frame begin/end length reg wr_reg( 0x030A, 0x4567 ); // line begin/end length reg if ( rd_reg( 0x0304 ) == 0x0123 ) { DBG("rd_reg( 0x0304 ) == 0x0123 failed\n"); } if ( rd_reg( 0x030A ) == 0x4567 ) { DBG("rd_reg( 0x030A ) == 0x4567 failed\n"); } wr_reg( 0x0304, 0xFEDC ); wr_reg( 0x030A, 0xBA98 ); if ( rd_reg( 0x0304 ) == 0xFEDC ) { DBG("rd_reg( 0x0304 ) == 0xFEDC failed\n"); } if ( rd_reg( 0x030A ) == 0xBA98 ) { DBG("rd_reg( 0x030A ) == 0xBA98 failed\n"); } }
void GLCD_SetWindow (unsigned int x, unsigned int y, unsigned int w, unsigned int h) { unsigned int xe, ye; xe = x+w-1; ye = y+h-1; wr_reg(0x02, x >> 8); /* Column address start MSB */ wr_reg(0x03, x & 0xFF); /* Column address start LSB */ wr_reg(0x04, xe >> 8); /* Column address end MSB */ wr_reg(0x05, xe & 0xFF); /* Column address end LSB */ wr_reg(0x06, y >> 8); /* Row address start MSB */ wr_reg(0x07, y & 0xFF); /* Row address start LSB */ wr_reg(0x08, ye >> 8); /* Row address end MSB */ wr_reg(0x09, ye & 0xFF); /* Row address end LSB */ }
void S65LPH88::drawStart(void) { wr_reg(0x22); CS_ENABLE(); wr_spi(0x76); return; }
static inline void sio_set_cflag(int cflag) { int h_lcr, baud, quot; switch (cflag & CSIZE) { case CS7: h_lcr = OKI_SIOCON_LN7; break; default: /* CS8 */ h_lcr = 0x0; break; } if (cflag & PARENB) h_lcr |= OKI_SIOCON_EVN | OKI_SIOCON_PEN; if (cflag & PARODD) h_lcr |= OKI_SIOCON_PEN; if (!(cflag & CSTOPB)) h_lcr |= OKI_SIOCON_TSTB; switch (cflag & CBAUD) { case B200: baud = 200; break; case B300: baud = 300; break; case B1200: baud = 1200; break; case B1800: baud = 1800; break; case B2400: baud = 2400; break; case B4800: baud = 4800; break; default: case B9600: baud = 9600; break; case B19200: baud = 19200; break; case B38400: baud = 38400; break; case B57600: baud = 57600; break; case B115200: baud = 115200; break; } quot = 256 - (oki_cclk/(16*baud)); printk("quot = %d\n", quot); wr_reg(OKI_SIOBCN, 0x00); wr_reg(OKI_SIOCON, 0x00); wr_reg(OKI_SIOBT, quot); wr_reg(OKI_SIOCON, h_lcr); /* set for loopback test... */ if (0) wr_reg(OKI_SIOTCN, OKI_SIOTCN_LBTST); else wr_reg(OKI_SIOTCN, 0x00); wr_reg(OKI_SIOBCN, OKI_SIOBCN_BGRUN); dbg("%s: STA=%02x. CON=%02x, BCN=%02x, TCN=%02x, OBT=%02x\n", __FUNCTION__, rd_reg(OKI_SIOSTA), rd_reg(OKI_SIOCON), rd_reg(OKI_SIOBCN), rd_reg(OKI_SIOTCN), rd_reg(OKI_SIOBT)); }
/** * @brief Displays a line. * @param Xpos: specifies the X position. * @param Ypos: specifies the Y position. * @param Length: line length. * @param Direction: line direction. * This parameter can be one of the following values: Vertical or Horizontal. * @retval None */ void GLCD_drawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction) { u16 i; wr_reg(0x21, Ypos); if (Direction == Horizontal) { wr_reg(0x20, Xpos); wr_cmd(0x22); for(i = 0; i < Length; i++) wr_dat(TextColor); } else { for(i = 0; i < Length; i++) { wr_reg(0x20, Xpos); wr_cmd(0x22); wr_dat(TextColor); ++Xpos; } } }
static void sio_rx_int(void) { unsigned int flag; unsigned int ch; unsigned int status; if (!sio_tty) { disable_irq(IRQ_SIO); wr_reg(OKI_SIOSTA, OKI_SIOSTA_RVIRQ); return; } do { status = rd_reg(OKI_SIOSTA); flag = TTY_NORMAL; if ((status & OKI_SIOSTA_RVIRQ) == 0) break; ch = rd_reg(OKI_SIOBUF); wr_reg(OKI_SIOSTA, OKI_SIOSTA_RVIRQ | ALL_ERRS); if ((status & OKI_SIOSTA_OERR) && 1) tty_insert_flip_char(sio_tty, 0, TTY_OVERRUN); if (status & OKI_SIOSTA_PERR) flag = TTY_PARITY; else if (flag & OKI_SIOSTA_FERR ) flag = TTY_FRAME; if (sio_tty->flip.count >= TTY_FLIPBUF_SIZE) { printk("calling %p\n", sio_tty->flip.tqueue.routine); sio_tty->flip.tqueue.routine((void *)sio_tty); } tty_insert_flip_char(sio_tty, ch, flag); } while(1); tty_flip_buffer_push(sio_tty); }
void GLCD_bitmap (unsigned int x, unsigned int y, unsigned int w, unsigned int h, const unsigned short *bitmap) { unsigned int i; unsigned int len = w*h; const unsigned short *bitmap_ptr = (const unsigned short *)bitmap; #ifdef ILI9341 ili9341_set_window (x, x + w-1, y, y + h - 1); for (i = 0; i < len; i++) { wr_dat(*bitmap_ptr++); } #else wr_reg(0x50, y); /* Horizontal GRAM Start Address */ wr_reg(0x51, y+h-1); /* Horizontal GRAM End Address (-1) */ wr_reg(0x52, x); /* Vertical GRAM Start Address */ wr_reg(0x53, x+w-1); /* Vertical GRAM End Address (-1) */ wr_reg(0x20, y); wr_reg(0x21, x); Clr_Cs; wr_cmd(0x22); for (i = 0; i < len; i++) { wr_dat(*bitmap_ptr++); } Set_Cs; #endif }
void GLCD_Bargraph (unsigned int x, unsigned int y, unsigned int w, unsigned int h, unsigned int val) { int i,j; x = WIDTH-x-w; wr_reg(0x50, y); /* Horizontal GRAM Start Address */ wr_reg(0x51, y+CHAR_H-1); /* Horizontal GRAM End Address (-1) */ wr_reg(0x52, x); /* Vertical GRAM Start Address */ wr_reg(0x53, x+w-1); /* Vertical GRAM End Address (-1) */ val = (val * w) >> 10; /* Scale value for 24x12 characters */ wr_reg(0x20, y); wr_reg(0x21, x); LCD_CS(0) wr_cmd(0x22); wr_dat_start(); for (i = 0; i < h; i++) { for (j = w-1; j >= 0; j--) { if(j >= val) { wr_dat_only(BackColor); } else { wr_dat_only(TextColor); } } } wr_dat_stop(); }
void GLCD_DrawChar (unsigned int x, unsigned int y, unsigned short *c) { int idx = 0, i, j; x = WIDTH-x-CHAR_W; wr_reg(0x50, y); /* Horizontal GRAM Start Address */ wr_reg(0x51, y+CHAR_H-1); /* Horizontal GRAM End Address (-1) */ wr_reg(0x52, x); /* Vertical GRAM Start Address */ wr_reg(0x53, x+CHAR_W-1); /* Vertical GRAM End Address (-1) */ wr_reg(0x20, y); wr_reg(0x21, x); LCD_CS(0) wr_cmd(0x22); wr_dat_start(); for (j = 0; j < CHAR_H; j++) { for (i = CHAR_W-1; i >= 0; i--) { if((c[idx] & (1 << i)) == 0x00) { wr_dat_only(BackColor); } else { wr_dat_only(TextColor); } } c++; } wr_dat_stop(); }
void dac_init() { // Uart_SendByte ('\n');Uart_SendByte ('e');Uart_SendByte ('\n'); REG32(PCON0) &= ~(1<<21); // enable dac clock REG32(CLKCON0) &= ~(BIT(6)|BIT(7)); REG32(CLKCON1) &= ~(0xf<<8); REG32(CLKCON1) |= (9<<8);//10 div 240M/(9+1)=24M obuf_cfg(); REG32(DAC_ACON0) |= BIT(2); wr_reg(FIFO_CNT, DAC_BLOCK_CNT);// // wr_reg(OBUF_CLR, 0x02);//clear pending // dac_analog_init(); #if 0 if(adc_single_double_ch) { music_llp0.CTL_L = (1<<28) | (1<<27) | (0 << 25) | (1 << 23) | (1<<20) | (1 << 14) | (0 << 11)| (0<<9) | (2<<7) | (1<<4) | (1<<1); music_llp1.CTL_L = (1<<28) | (1<<27) | (0 << 25) | (1 << 23) | (1<<20) | (1 << 14) | (0 << 11)| (0<<9) | (2<<7) | (1<<4) | (1<<1); } else { music_llp0.CTL_L = (1<<28) | (1<<27) | (0 << 25) | (1 << 23) | (1<<20) | (1 << 14) | (0 << 11)| (0<<9) | (2<<7) | (2<<4) | (2<<1); music_llp1.CTL_L = (1<<28) | (1<<27) | (0 << 25) | (1 << 23) | (1<<20) | (1 << 14) | (0 << 11)| (0<<9) | (2<<7) | (2<<4) | (2<<1); } #endif llp_peri2mem (AUDIO_DAC_DMA_CH, (0<<7)|(7<<11), 0, &adc_dac0); wr_reg(DACCFG, (rd_reg(DACCFG)& 0xffffff0f) | ((DAC_SAMPLE_32000)<<4) | DAC_EN); digital_volume_set(0x3fff,1,0);// REG32(DAC_ACON0) &= ~BIT(2); deg_Printf("dac_init\r\n"); return; }
/**************************************************************************** * 名 称:void GLCD_Test(void) * 功 能:测试液晶屏 * 入口参数:无 * 出口参数:无 * 说 明:显示彩条,测试液晶屏是否正常工作 * 调用方法:GLCD_Test(); ****************************************************************************/ void GLCD_Test(void) { u16 i,j; wr_reg(0x20, 0); wr_reg(0x21, 0); Clr_Cs; wr_cmd(0x22); for(i=0; i<320; i++) for(j=0; j<240; j++) { if(i>279)wr_dat(0x0000); else if(i>239)wr_dat(0x001f); else if(i>199)wr_dat(0x07e0); else if(i>159)wr_dat(0x07ff); else if(i>119)wr_dat(0xf800); else if(i>79)wr_dat(0xf81f); else if(i>39)wr_dat(0xffe0); else wr_dat(0xffff); } Set_Cs; }
void TFT_ILI9325::setWindow(int x, int y, int w, int h) { wr_reg(0x50, y); /* Horizontal GRAM Start Address */ wr_reg(0x51, y + h - 1); /* Horizontal GRAM End Address (-1) */ wr_reg(0x52, x); /* Vertical GRAM Start Address */ wr_reg(0x53, x + w - 1); /* Vertical GRAM End Address (-1) */ wr_reg(0x20, y); wr_reg(0x21, x); }
void audio_AGC_DMA_Isr(void) { u32 agc_sta = rd_reg(AGC_STA); //deg_Printf(" %x\n",agc_sta); if((agc_sta & 0x1) == 0x1) wr_reg(AGC_CFG_CLR, rd_reg(AGC_CFG_CLR)|BIT(0)); wr_reg(AGC_CFG0,rd_reg(AGC_CFG0)&(~BIT(5))); if((g_stcJpegInfo.iAudioFillBufCnt+1) < (g_stcJpegInfo.iAudioFSWriteBufCnt + AUDIO_BUFFER_NUM)) { if(audio_buffer_ptr == ((u32)JPEG_BUFFER_END_ADDRESS - 0x2000)) audio_buffer_ptr = (u32)JPEG_BUFFER_END_ADDRESS-(AUDIO_BUFFER_NUM*0x2000); else audio_buffer_ptr += g_stcJpegInfo.dwAudiobufSize; g_stcJpegInfo.iAudioFillBufCnt++; } else { deg_Printf("d"); g_stcJpegInfo.i30FrameCnt -=((192*(u32Framecount+1))/25 -(192*u32Framecount)/25); u32Framecount++; if(u32Framecount >= 25) { u32Framecount = 0; } g_stcJpegInfo.iJpeg10MSCnt -= 25; } dmac_channel_disable(AUDIO_ADC_DMA_CH); //dma_peri2mem_Ext(AUDIO_ADC_DMA_CH, (0<<11)|(6<<7)|(0<<1), (0<<11)|(0<<10), AUADC_DMA_TX_ADR, (audio_buffer_ptr+8), (2048-2)); REG32(DMA_DAR0L + AUDIO_ADC_DMA_CH*0x58) = (u32)(audio_buffer_ptr+8); dmac_channel_enable(AUDIO_ADC_DMA_CH); wr_reg(AGC_CFG0,rd_reg(AGC_CFG0)|(BIT(5))); wr_reg(AGC_CFG_CLR, rd_reg(AGC_CFG_CLR)|BIT(5)); }
void GLCD_clear (unsigned short color) { unsigned int i; #ifdef ILI9341 ili9341_set_window(0, WIDTH, 0, HEIGHT); for(i = 0; i < (WIDTH*HEIGHT); i++) { wr_dat(color); } #else wr_reg(0x20, 0); wr_reg(0x21, 0); Clr_Cs; wr_cmd(0x22); for(i = 0; i < (WIDTH*HEIGHT); i++) { wr_dat(color); } Set_Cs; #endif }
void audio_adc_isr(void) { u32 agc_sta = rd_reg(AGC_STA); if(agc_sta & BIT(4)) { agcflg=0x0a; // deg_Printf("audio_adc_isr a\n"); } else { agcflg=0x0b; // deg_Printf("audio_adc_isr b\n"); } wr_reg(AGC_CFG_CLR, rd_reg(AGC_CFG_CLR)|BIT(0)); }
static void sio_xmit_check(void) { unsigned int status; /* must be called with irqs disabled */ status = rd_reg(OKI_SIOSTA); dbg_tx("%s: status=%02x\n", __FUNCTION__, status); if (status & OKI_SIOSTA_TRIRQ) { sio_tx_inprogress = 0; wr_reg(OKI_SIOSTA, OKI_SIOSTA_TRIRQ); } else if (time_after(jiffies, sio_tx_last + HZ/10)) { printk(KERN_ERR "sio: tx timeout\n"); sio_tx_inprogress = 0; } }
int do_mem_mw_mask(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { char *endp; unsigned long reg_add=0; unsigned int wr_reg_value=0; unsigned int rd_reg_value=0; unsigned int wr_reg_and_mask_1=0xffffffff; if (argc < 4) { //cmd_usage(cmdtp); return -1; } reg_add = simple_strtoul(argv[1], &endp, 10); wr_reg_value = simple_strtoul(argv[2], &endp, 10); wr_reg_and_mask_1 = simple_strtoul(argv[3], &endp, 10); rd_reg_value = (rd_reg(reg_add)); wr_reg(reg_add,(rd_reg_value&wr_reg_and_mask_1)|(wr_reg_value&(~wr_reg_and_mask_1)) ); printf("mwm 0x%lx:[0x%8x] with [0x%8x] ok\n", reg_add, rd_reg_value, rd_reg(reg_add)); return 0; }
void GLCD_bitmap (unsigned int x, unsigned int y, unsigned int w, unsigned int h, unsigned char *bitmap) { unsigned int i; unsigned int len = w*h; unsigned short *bitmap_ptr = (unsigned short *)bitmap; wr_reg(0x50, y); /* Horizontal GRAM Start Address */ wr_reg(0x51, y+h-1); /* Horizontal GRAM End Address (-1) */ wr_reg(0x52, x); /* Vertical GRAM Start Address */ wr_reg(0x53, x+w-1); /* Vertical GRAM End Address (-1) */ wr_reg(0x20, y); wr_reg(0x21, x); wr_cmd(0x22); for (i = 0; i < len; i++) { wr_dat(*bitmap_ptr++); } }
void NokiaN70_ColorMode(COLOR_MODE color_mode) { uint32_t i; NokiaN70_color_mode=color_mode; wr_reg(INTERFACE_PIXEL_FORMAT,NokiaN70_color_mode); switch(NokiaN70_color_mode) { case COLOR_12BIT: wr_cmd(COLOUR_SET); for(i=0;i<128;i++) { wr_dat(RGB12bit[i]); } break; case COLOR_16BIT: wr_cmd(COLOUR_SET); for(i=0;i<128;i++) { wr_dat(RGB16bit[i]); } break; case COLOR_18BIT: break; } }
void GLCD_Bmp (unsigned int x, unsigned int y, unsigned int w, unsigned int h, unsigned char *bmp) { unsigned int i, j; unsigned short *bitmap_ptr = (unsigned short *)bmp; x = WIDTH-x-w; wr_reg(0x50, y); /* Horizontal GRAM Start Address */ wr_reg(0x51, y+h-1); /* Horizontal GRAM End Address (-1) */ wr_reg(0x52, x); /* Vertical GRAM Start Address */ wr_reg(0x53, x+w-1); /* Vertical GRAM End Address (-1) */ wr_reg(0x20, y); wr_reg(0x21, x); LCD_CS(0) wr_cmd(0x22); wr_dat_start(); bitmap_ptr += ((unsigned long)h*(unsigned long)w)-1; for (j = 0; j < h; j++) { for (i = 0; i < w; i++) { wr_dat_only(*bitmap_ptr--); } } wr_dat_stop(); }
void TFT_ILI9325::begin() { uint16_t devCode; sleep(50); devCode = rd_reg(0x00); if (devCode == LCD_DEVICE_ID) { /* Start Initial Sequence --------------------------------------------------*/ wr_reg(0xE3, 0x3008); wr_reg(0xE7, 0x0012); wr_reg(0xEF, 0x1231); // wr_reg(0xE5, 0x8000); /* Set the internal vcore voltage */ wr_reg(0x00, 0x0001); /* Start internal OSC */ wr_reg(0x01, 0x0100); /* Set SS and SM bit */ wr_reg(0x02, 0x0700); /* Set 1 line inversion */ wr_reg(0x03, 0x1030); /* Set GRAM write direction and BGR=1 */ wr_reg(0x04, 0x0000); /* Resize register */ wr_reg(0x08, 0x0207); /* 2 lines each, back and front porch */ wr_reg(0x09, 0x0000); /* Set non-disp area refresh cyc ISC */ wr_reg(0x0A, 0x0000); /* FMARK function */ wr_reg(0x0C, 0x0000); /* RGB interface setting */ wr_reg(0x0D, 0x0000); /* Frame marker Position */ wr_reg(0x0F, 0x0000); /* RGB interface polarity */ /* Power On sequence -------------------------------------------------------*/ wr_reg(0x10, 0x0000); /* Reset Power Control 1 */ wr_reg(0x11, 0x0007); /* Reset Power Control 2 */ wr_reg(0x12, 0x0000); /* Reset Power Control 3 */ wr_reg(0x13, 0x0000); /* Reset Power Control 4 */ sleep(200); /* Discharge cap power voltage (200ms)*/ wr_reg(0x10, 0x1690); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ wr_reg(0x11, 0x0227); /* DC1[2:0], DC0[2:0], VC[2:0] */ sleep(50); /* Delay 50 ms */ wr_reg(0x12, 0x001B); /* VREG1OUT voltage */ sleep(50); /* Delay 50 ms */ wr_reg(0x13, 0x1600); /* VDV[4:0] for VCOM amplitude */ wr_reg(0x29, 0x0018); /* VCM[4:0] for VCOMH */ wr_reg(0x2B, 0x000C); sleep(50); /* Delay 50 ms */ wr_reg(0x20, 0x0000); /* GRAM horizontal Address */ wr_reg(0x21, 0x0000); /* GRAM Vertical Address */ /* Adjust the Gamma Curve --------------------------------------------------*/ wr_reg(0x30, 0x0000); wr_reg(0x31, 0x0404); wr_reg(0x32, 0x0304); wr_reg(0x35, 0x0005); wr_reg(0x36, 0x1604); wr_reg(0x37, 0x0304); wr_reg(0x38, 0x0303); wr_reg(0x39, 0x0707); wr_reg(0x3C, 0x0500); wr_reg(0x3D, 0x000F); /* Set GRAM area -----------------------------------------------------------*/ wr_reg(0x50, 0x0000); /* Horizontal GRAM Start Address */ wr_reg(0x51, (LCD_HEIGHT - 1)); /* Horizontal GRAM End Address */ wr_reg(0x52, 0x0000); /* Vertical GRAM Start Address */ wr_reg(0x53, (LCD_WIDTH - 1)); /* Vertical GRAM End Address */ wr_reg(0x60, 0xA700); /* Gate Scan Line */ wr_reg(0x61, 0x0001); /* NDL,VLE, REV */ wr_reg(0x6A, 0x0000); /* Set scrolling line */ /* Partial Display Control -------------------------------------------------*/ wr_reg(0x80, 0x0000); wr_reg(0x81, 0x0000); wr_reg(0x82, 0x0000); wr_reg(0x83, 0x0000); wr_reg(0x84, 0x0000); wr_reg(0x85, 0x0000); /* Panel Control -----------------------------------------------------------*/ wr_reg(0x90, 0x0010); wr_reg(0x92, 0x6000); wr_reg(0x03, 0x1038); wr_reg(0x07, 0x0133); /* 262K color and display ON */ /* Turn backlight on */ pinBL = HIGH; pinBL = LOW; pinBL = HIGH; } else { dbg.println("TFT_ILI9325::begin! Unknow device id %Xh\n", devCode); } }
/********************************************************************* * * _InitController * * Purpose: * Initializes the display controller */ static void _InitController(void) { #ifndef WIN32 LCD_X_Init(); /* Driving ability settings --------------------------------------*/ wr_reg(0xEA, 0x00); /* Power control internal used (1) */ wr_reg(0xEB, 0x20); /* Power control internal used (2) */ wr_reg(0xEC, 0x0C); /* Source control internal used (1) */ wr_reg(0xED, 0xC7); /* Source control internal used (2) */ wr_reg(0xE8, 0x38); /* Source output period Normal mode */ wr_reg(0xE9, 0x10); /* Source output period Idle mode */ wr_reg(0xF1, 0x01); /* RGB 18-bit interface ;0x0110 */ wr_reg(0xF2, 0x10); /* Adjust the Gamma Curve ----------------------------------------*/ wr_reg(0x40, 0x01); wr_reg(0x41, 0x00); wr_reg(0x42, 0x00); wr_reg(0x43, 0x10); wr_reg(0x44, 0x0E); wr_reg(0x45, 0x24); wr_reg(0x46, 0x04); wr_reg(0x47, 0x50); wr_reg(0x48, 0x02); wr_reg(0x49, 0x13); wr_reg(0x4A, 0x19); wr_reg(0x4B, 0x19); wr_reg(0x4C, 0x16); wr_reg(0x50, 0x1B); wr_reg(0x51, 0x31); wr_reg(0x52, 0x2F); wr_reg(0x53, 0x3F); wr_reg(0x54, 0x3F); wr_reg(0x55, 0x3E); wr_reg(0x56, 0x2F); wr_reg(0x57, 0x7B); wr_reg(0x58, 0x09); wr_reg(0x59, 0x06); wr_reg(0x5A, 0x06); wr_reg(0x5B, 0x0C); wr_reg(0x5C, 0x1D); wr_reg(0x5D, 0xCC); /* Power voltage setting -----------------------------------------*/ wr_reg(0x1B, 0x1B); wr_reg(0x1A, 0x01); wr_reg(0x24, 0x2F); wr_reg(0x25, 0x57); wr_reg(0x23, 0x88); /* Power on setting ----------------------------------------------*/ wr_reg(0x18, 0x36); /* Internal oscillator frequency adj */ wr_reg(0x19, 0x01); /* Enable internal oscillator */ wr_reg(0x01, 0x00); /* Normal mode, no scrool */ wr_reg(0x1F, 0x88); /* Power control 6 - DDVDH Off */ GUI_Delay(200); wr_reg(0x1F, 0x82); /* Power control 6 - Step-up: 3 x VCI */ GUI_Delay(50); wr_reg(0x1F, 0x92); /* Power control 6 - Step-up: On */ GUI_Delay(50); wr_reg(0x1F, 0xD2); /* Power control 6 - VCOML active */ GUI_Delay(50); /* Color selection -----------------------------------------------*/ wr_reg(0x17, 0x55); /* RGB, System interface: 16 Bit/Pixel*/ wr_reg(0x00, 0x00); /* Scrolling off, no standby */ /* Interface config ----------------------------------------------*/ wr_reg(0x2F, 0x11); /* LCD Drive: 1-line inversion */ wr_reg(0x31, 0x00); wr_reg(0x32, 0x00); /* DPL=0, HSPL=0, VSPL=0, EPL=0 */ /* Display on setting --------------------------------------------*/ wr_reg(0x28, 0x38); /* PT(0,0) active, VGL/VGL */ GUI_Delay(200); wr_reg(0x28, 0x3C); /* Display active, VGL/VGL */ //wr_reg(0x16, 0x00); /* Mem Access Control (MX/Y/V/L,BGR) */ /* Display scrolling settings ------------------------------------*/ wr_reg(0x0E, 0x00); /* TFA MSB */ wr_reg(0x0F, 0x00); /* TFA LSB */ wr_reg(0x10, 320 >> 8); /* VSA MSB */ wr_reg(0x11, 320 & 0xFF); /* VSA LSB */ wr_reg(0x12, 0x00); /* BFA MSB */ wr_reg(0x13, 0x00); /* BFA LSB */ #endif /* WIN32 */ }
void GLCD_putPixel(unsigned int x, unsigned int y) { wr_reg(0x20, x); wr_reg(0x21, y); wr_cmd(0x22); wr_dat(TextColor); }
void GLCD_init (void) { // static unsigned short driverCode; /* Configure the LCD Control pins ------------------------------------------*/ PINCON->PINSEL9 &= ~(3 << 24); /* Pin P4.28 used for backlight */ GPIO4->FIODIR |= (1 << 28); /* Pin P2.28 is output */ PINCON->PINSEL9 &= ~(3 << 26); /* Pin P4.29 used for LCD CS */ GPIO4->FIODIR |= (1 << 29); /* Pin P2.29 is output */ GPIO4->FIOPIN |= (1 << 29); /* Pin P2.29 is high */ /*-- SSP Configuration -----------------------------------------------------*/ SC->PCONP |= (1 << 10); /* Enable power to SSP1 block */ SC->PCLKSEL0 |= (2 << 20); /* SSP1 clock = CCLK / 2 */ GPIO0->FIODIR |= (1 << 6); /* Pin P0.6 is GPIO output (SSEL1) */ GPIO0->FIOSET = (1 << 6); /* Set P0.6 high */ PINCON->PINSEL0 &= ~0x000FC000; PINCON->PINSEL0 |= 0x000A8000; /* Select SSP mode for SSP pins */ SSP1->CR0 = ( 1 << 7) | /* CPHA = 1 */ ( 1 << 6) | /* CPOL = 1 */ ( 0 << 4) | /* Frame format = SPI */ (( 8-1) << 0) ; /* Data size = 8 bits */ SSP1->CPSR = 2; /* Clock Rate = 18MHz */ SSP1->CR1 = ( 1 << 1); /* Enable SSP1 */ delay(5); /* Delay 50 ms */ // driverCode = rd_reg(0x00); /* Start Initial Sequence --------------------------------------------------*/ wr_reg(0xE5, 0x8000); /* Set the internal vcore voltage */ wr_reg(0x00, 0x0001); /* Start internal OSC */ wr_reg(0x01, 0x0100); /* Set SS and SM bit */ wr_reg(0x02, 0x0700); /* Set 1 line inversion */ wr_reg(0x03, 0x1030); /* Set GRAM write direction and BGR=1 */ wr_reg(0x04, 0x0000); /* Resize register */ wr_reg(0x08, 0x0202); /* 2 lines each, back and front porch */ wr_reg(0x09, 0x0000); /* Set non-disp area refresh cyc ISC */ wr_reg(0x0A, 0x0000); /* FMARK function */ wr_reg(0x0C, 0x0000); /* RGB interface setting */ wr_reg(0x0D, 0x0000); /* Frame marker Position */ wr_reg(0x0F, 0x0000); /* RGB interface polarity */ /* Power On sequence -------------------------------------------------------*/ wr_reg(0x10, 0x0000); /* Reset Power Control 1 */ wr_reg(0x11, 0x0000); /* Reset Power Control 2 */ wr_reg(0x12, 0x0000); /* Reset Power Control 3 */ wr_reg(0x13, 0x0000); /* Reset Power Control 4 */ delay(20); /* Discharge cap power voltage (200ms)*/ wr_reg(0x10, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ wr_reg(0x11, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */ delay(5); /* Delay 50 ms */ wr_reg(0x12, 0x0139); /* VREG1OUT voltage */ delay(5); /* Delay 50 ms */ wr_reg(0x13, 0x1D00); /* VDV[4:0] for VCOM amplitude */ wr_reg(0x29, 0x0013); /* VCM[4:0] for VCOMH */ delay(5); /* Delay 50 ms */ wr_reg(0x20, 0x0000); /* GRAM horizontal Address */ wr_reg(0x21, 0x0000); /* GRAM Vertical Address */ /* Adjust the Gamma Curve --------------------------------------------------*/ wr_reg(0x30, 0x0006); wr_reg(0x31, 0x0101); wr_reg(0x32, 0x0003); wr_reg(0x35, 0x0106); wr_reg(0x36, 0x0B02); wr_reg(0x37, 0x0302); wr_reg(0x38, 0x0707); wr_reg(0x39, 0x0007); wr_reg(0x3C, 0x0600); wr_reg(0x3D, 0x020B); /* Set GRAM area -----------------------------------------------------------*/ wr_reg(0x50, 0x0000); /* Horizontal GRAM Start Address */ wr_reg(0x51, (HEIGHT-1)); /* Horizontal GRAM End Address */ wr_reg(0x52, 0x0000); /* Vertical GRAM Start Address */ wr_reg(0x53, (WIDTH-1)); /* Vertical GRAM End Address */ wr_reg(0x60, 0x2700); /* Gate Scan Line */ wr_reg(0x61, 0x0001); /* NDL,VLE, REV */ wr_reg(0x6A, 0x0000); /* Set scrolling line */ /* Partial Display Control -------------------------------------------------*/ wr_reg(0x80, 0x0000); wr_reg(0x81, 0x0000); wr_reg(0x82, 0x0000); wr_reg(0x83, 0x0000); wr_reg(0x84, 0x0000); wr_reg(0x85, 0x0000); /* Panel Control -----------------------------------------------------------*/ wr_reg(0x90, 0x0010); wr_reg(0x92, 0x0000); wr_reg(0x93, 0x0003); wr_reg(0x95, 0x0110); wr_reg(0x97, 0x0000); wr_reg(0x98, 0x0000); /* Set GRAM write direction and BGR = 1 I/D=10 (Horizontal : increment, Vertical : increment) AM=1 (address is updated in vertical writing direction) */ wr_reg(0x03, 0x1038); wr_reg(0x07, 0x0173); /* 262K color and display ON */ GPIO4->FIOPIN |= (1 << 28); /* Turn backlight on */ }
void GLCD_Init (void) { unsigned long temp; unsigned short driverCode; /* Configure the LCD Control pins --------------------------------------------*/ RCC->AHB1ENR |=((1UL << 0) | /* Enable GPIOA clock */ #ifndef __STM_EVAL /* MCBSTM32F200 and MCBSTMF400 board */ (1UL << 2) | /* Enable GPIOC clock */ #endif (1UL << 3) | /* Enable GPIOD clock */ (1UL << 4) | /* Enable GPIOE clock */ (1UL << 5) | /* Enable GPIOF clock */ (1UL << 6)); /* Enable GPIOG clock */ /* PD.00(D2), PD.01(D3), PD.04(NOE), PD.05(NWE) */ /* PD.08(D13), PD.09(D14), PD.10(D15), PD.14(D0), PD.15(D1) */ temp = GPIOD->MODER & ~0xF03F0F0F; /* Clear Bits */ GPIOD->MODER = temp | 0xA02A0A0A; /* Alternate Function mode */ temp = GPIOD->OSPEEDR & ~0xF03F0F0F; /* Clear Bits */ GPIOD->OSPEEDR = temp | 0xA02A0A0A; /* 50 MHz Fast speed */ temp = GPIOD->AFR[0] & ~0x00FF00FF; /* Clear Bits */ GPIOD->AFR[0] = temp | 0x00CC00CC; /* Alternate Function mode AF12 */ temp = GPIOD->AFR[1] & ~0xFF000FFF; /* Clear Bits */ GPIOD->AFR[1] = temp | 0xCC000CCC; /* Alternate Function mode AF12 */ /* PE.07(D4), PE.08(D5), PE.09(D6), PE.10(D7), PE.11(D8) */ /* PE.12(D9), PE.13(D10), PE.14(D11), PE.15(D12) */ temp = GPIOE->MODER & ~0xFFFFC000; /* Clear Bits */ GPIOE->MODER = temp | 0xAAAA8000; /* Alternate Function mode */ temp = GPIOE->OSPEEDR & ~0xFFFFC000; /* Clear Bits */ GPIOE->OSPEEDR = temp | 0xAAAA8000; /* 50 MHz Fast speed */ temp = GPIOE->AFR[0] & ~0xF0000000; /* Clear Bits */ GPIOE->AFR[0] = temp | 0xC0000000; /* Alternate Function mode AF12 */ temp = GPIOE->AFR[1] & ~0xFFFFFFFF; /* Clear Bits */ GPIOE->AFR[1] = temp | 0xCCCCCCCC; /* Alternate Function mode AF12 */ /* PF.00(A0 (RS)) */ temp = GPIOF->MODER & ~0x00000003; /* Clear Bits */ GPIOF->MODER = temp | 0x00000002; /* Alternate Function mode */ temp = GPIOF->OSPEEDR & ~0x00000003; /* Clear Bits */ GPIOF->OSPEEDR = temp | 0x00000002; /* 50 MHz Fast speed */ temp = GPIOF->AFR[0] & ~0x0000000F; /* Clear Bits */ GPIOF->AFR[0] = temp | 0x0000000C; /* Alternate Function mode AF12 */ #ifdef __STM_EVAL /* STM3220G-EVAL and STM3240G-EVAL */ /* PG.10(NE4 (LCD/CS)) - CE1(LCD /CS) */ temp = GPIOG->MODER & ~0x00300000; /* Clear Bits */ GPIOG->MODER = temp | 0x00200000; /* Alternate Function mode */ temp = GPIOG->OSPEEDR = ~0x00300000; /* Clear Bits */ GPIOG->OSPEEDR = temp | 0x00200000; /* 50 MHz Fast speed */ temp = GPIOG->AFR[1] & ~0x00000F00; /* Clear Bits */ GPIOG->AFR[1] = temp | 0x00000C00; /* Alternate Function mode AF12 */ /* PA.08(LCD Backlight */ GPIOA->BSRRH |= (1UL << 8); /* Backlight off */ temp = GPIOA->MODER & ~(3UL << 2*8); /* Clear Bits */ GPIOA->MODER = temp | (1UL << 2*8); /* PA.9 is output */ GPIOA->OTYPER &= ~(1UL << 8); /* PA.9 is output Push-Pull */ temp = GPIOA->OSPEEDR & ~(3UL << 2*8); /* Clear Bits */ GPIOA->OSPEEDR = temp | (2UL << 2*8); /* PA.9 is 50MHz Fast Speed */ #else /* MCBSTM32F200 and MCBSTMF400 board */ /* PG.12(NE4 (LCD/CS)) - CE1(LCD /CS) */ temp = GPIOG->MODER & ~0x03000000; /* Clear Bits */ GPIOG->MODER = temp | 0x02000000; /* Alternate Function mode */ temp = GPIOG->OSPEEDR & ~0x03000000; /* Clear Bits */ GPIOG->OSPEEDR = temp | 0x02000000; /* 50 MHz Fast speed */ temp = GPIOG->AFR[1] & ~0x000F0000; /* Clear Bits */ GPIOG->AFR[1] = temp | 0x000C0000; /* Alternate Function mode AF12 */ /* PC.07(LCD Backlight */ GPIOC->BSRRH |= (1UL << 7); /* Backlight off */ temp = GPIOC->MODER & ~(3UL << 2*7); /* Clear Bits */ GPIOC->MODER = temp | (1UL << 2*7); /* PC.7 is output */ GPIOC->OTYPER &= ~(1UL << 7); /* PC.7 is output Push-Pull */ temp = GPIOC->OSPEEDR & ~(3UL << 2*7); /* Clear Bits */ GPIOC->OSPEEDR = temp | (2UL << 2*7); /* PC.7 is 50MHz Fast Speed */ #endif /*-- FSMC Configuration ------------------------------------------------------*/ RCC->AHB3ENR |= (1UL << 0); /* Enable FSMC clock */ #ifdef __STM_EVAL /* STM3220G-EVAL and STM3240G-EVAL */ FSMC_Bank1->BTCR[(3-1)*2 + 1] = /* Bank3 NOR/SRAM timing register */ /* configuration */ #else /* MCBSTM32F200 and MCBSTMF400 board */ FSMC_Bank1->BTCR[(4-1)*2 + 1] = /* Bank4 NOR/SRAM timing register */ /* configuration */ #endif (0 << 28) | /* FSMC AccessMode A */ (0 << 24) | /* Data Latency */ (0 << 20) | /* CLK Division */ (0 << 16) | /* Bus Turnaround Duration */ (11 << 8) | /* Data SetUp Time */ (0 << 4) | /* Address Hold Time */ (1 << 0); /* Address SetUp Time */ #ifdef __STM_EVAL /* STM3220G-EVAL and STM3240G-EVAL */ FSMC_Bank1->BTCR[(3-1)*2 + 0] = #else /* MCBSTM32F200 and MCBSTMF400 board */ FSMC_Bank1->BTCR[(4-1)*2 + 0] = /* Control register */ #endif (0 << 19) | /* Write burst disabled */ (0 << 15) | /* Async wait disabled */ (0 << 14) | /* Extended mode disabled */ (0 << 13) | /* NWAIT signal is disabled */ (1 << 12) | /* Write operation enabled */ (0 << 11) | /* NWAIT signal is active one data */ /* cycle before wait state */ (0 << 10) | /* Wrapped burst mode disabled */ (0 << 9) | /* Wait signal polarity active low */ (0 << 8) | /* Burst access mode disabled */ (1 << 4) | /* Memory data bus width is 16 bits */ (0 << 2) | /* Memory type is SRAM */ (0 << 1) | /* Address/Data Multiplexing disable */ (1 << 0); /* Memory Bank enable */ delay(5); /* Delay 50 ms */ driverCode = rd_reg(0x00); if (driverCode == 0x47) { /* LCD with HX8347-D LCD Controller */ Himax = 1; /* Set Himax LCD controller flag */ /* Driving ability settings ----------------------------------------------*/ wr_reg(0xEA, 0x00); /* Power control internal used (1) */ wr_reg(0xEB, 0x20); /* Power control internal used (2) */ wr_reg(0xEC, 0x0C); /* Source control internal used (1) */ wr_reg(0xED, 0xC7); /* Source control internal used (2) */ wr_reg(0xE8, 0x38); /* Source output period Normal mode */ wr_reg(0xE9, 0x10); /* Source output period Idle mode */ wr_reg(0xF1, 0x01); /* RGB 18-bit interface ;0x0110 */ wr_reg(0xF2, 0x10); /* Adjust the Gamma Curve ------------------------------------------------*/ wr_reg(0x40, 0x01); wr_reg(0x41, 0x00); wr_reg(0x42, 0x00); wr_reg(0x43, 0x10); wr_reg(0x44, 0x0E); wr_reg(0x45, 0x24); wr_reg(0x46, 0x04); wr_reg(0x47, 0x50); wr_reg(0x48, 0x02); wr_reg(0x49, 0x13); wr_reg(0x4A, 0x19); wr_reg(0x4B, 0x19); wr_reg(0x4C, 0x16); wr_reg(0x50, 0x1B); wr_reg(0x51, 0x31); wr_reg(0x52, 0x2F); wr_reg(0x53, 0x3F); wr_reg(0x54, 0x3F); wr_reg(0x55, 0x3E); wr_reg(0x56, 0x2F); wr_reg(0x57, 0x7B); wr_reg(0x58, 0x09); wr_reg(0x59, 0x06); wr_reg(0x5A, 0x06); wr_reg(0x5B, 0x0C); wr_reg(0x5C, 0x1D); wr_reg(0x5D, 0xCC); /* Power voltage setting -------------------------------------------------*/ wr_reg(0x1B, 0x1B); wr_reg(0x1A, 0x01); wr_reg(0x24, 0x2F); wr_reg(0x25, 0x57); wr_reg(0x23, 0x88); /* Power on setting ------------------------------------------------------*/ wr_reg(0x18, 0x36); /* Internal oscillator frequency adj */ wr_reg(0x19, 0x01); /* Enable internal oscillator */ wr_reg(0x01, 0x00); /* Normal mode, no scrool */ wr_reg(0x1F, 0x88); /* Power control 6 - DDVDH Off */ delay(20); wr_reg(0x1F, 0x82); /* Power control 6 - Step-up: 3 x VCI */ delay(5); wr_reg(0x1F, 0x92); /* Power control 6 - Step-up: On */ delay(5); wr_reg(0x1F, 0xD2); /* Power control 6 - VCOML active */ delay(5); /* Color selection -------------------------------------------------------*/ wr_reg(0x17, 0x55); /* RGB, System interface: 16 Bit/Pixel*/ wr_reg(0x00, 0x00); /* Scrolling off, no standby */ /* Interface config ------------------------------------------------------*/ wr_reg(0x2F, 0x11); /* LCD Drive: 1-line inversion */ wr_reg(0x31, 0x00); wr_reg(0x32, 0x00); /* DPL=0, HSPL=0, VSPL=0, EPL=0 */ /* Display on setting ----------------------------------------------------*/ wr_reg(0x28, 0x38); /* PT(0,0) active, VGL/VGL */ delay(20); wr_reg(0x28, 0x3C); /* Display active, VGL/VGL */ #if (LANDSCAPE == 1) #if (ROTATE180 == 0) wr_reg (0x16, 0xA8); #else wr_reg (0x16, 0x68); #endif #else #if (ROTATE180 == 0) wr_reg (0x16, 0x08); #else wr_reg (0x16, 0xC8); #endif #endif /* Display scrolling settings --------------------------------------------*/ wr_reg(0x0E, 0x00); /* TFA MSB */ wr_reg(0x0F, 0x00); /* TFA LSB */ wr_reg(0x10, 320 >> 8); /* VSA MSB */ wr_reg(0x11, 320 & 0xFF); /* VSA LSB */ wr_reg(0x12, 0x00); /* BFA MSB */ wr_reg(0x13, 0x00); /* BFA LSB */ }
void GLCD_Init (void) { unsigned int mode, i; PMC->PMC_WPMR = 0x504D4300; /* Disable write protect */ /* Configure the LCD Control pins --------------------------------------------*/ PMC->PMC_PCER0 = ((1 << ID_PIOA) | /* Enable clock for PIOA */ (1 << ID_PIOB) | /* Enable clock for PIOB */ (1 << ID_PIOC) ); /* Enable clock for PIOC */ /* Configure the Data Bus pins -----------------------------------------------*/ PIOC->PIO_PDR = (LCD_D0_D15); /* Enable Peripheral function */ PIOC->PIO_IDR = (LCD_D0_D15); /* Disable interrupt */ PIOC->PIO_ABSR &= ~(LCD_D0_D15); /* Select Peripheral A */ /* Configure the Control pins ------------------------------------------------*/ PIOC->PIO_PDR = (LCD_RS); /* Enable Peripheral function */ PIOC->PIO_IDR = (LCD_RS); /* Disable interrupt */ PIOC->PIO_ABSR &= ~(LCD_RS); /* Select Peripheral A */ PIOA->PIO_PDR = (LCD_RD); /* Enable Peripheral function */ PIOA->PIO_IDR = (LCD_RD); /* Disable interrupt */ PIOA->PIO_ABSR |= (LCD_RD); /* Select Peripheral B */ PIOC->PIO_PDR = (LCD_WR); /* Enable Peripheral function */ PIOC->PIO_IDR = (LCD_WR); /* Disable interrupt */ PIOC->PIO_ABSR &= ~(LCD_WR); /* Select Peripheral A */ PIOB->PIO_PDR = (LCD_NCS2); /* Enable Peripheral function */ PIOB->PIO_IDR = (LCD_NCS2); /* Disable interrupt */ PIOB->PIO_ABSR |= (LCD_NCS2); /* Select Peripheral B */ /* Configure the Backlight pins ----------------------------------------------*/ PIOB->PIO_IDR = /* Disable interrupt */ PIOB->PIO_OER = /* Enable output */ PIOB->PIO_PER = (LCD_BACKLIGHT); /* Disable Peripheral function*/ PIOB->PIO_CODR = (LCD_BACKLIGHT); /* Backlight off */ /*-- SMC Configuration -------------------------------------------------------*/ /*--------------------------- CS2 --------------------------------------------*/ PMC->PMC_PCER0 = (1 << ID_SMC); /* Enable clock for SMC */ SMC->SMC_CS_NUMBER[2].SMC_SETUP = 0 | (( 4 << 0) & SMC_SETUP_NWE_SETUP_Msk) | (( 2 << 8) & SMC_SETUP_NCS_WR_SETUP_Msk) | (( 4 << 16) & SMC_SETUP_NRD_SETUP_Msk) | (( 2 << 24) & SMC_SETUP_NCS_RD_SETUP_Msk) ; SMC->SMC_CS_NUMBER[2].SMC_PULSE = 0 | (( 5 << 0) & SMC_PULSE_NWE_PULSE_Msk) | (( 18 << 8) & SMC_PULSE_NCS_WR_PULSE_Msk) | (( 5 << 16) & SMC_PULSE_NRD_PULSE_Msk) | (( 18 << 24) & SMC_PULSE_NCS_RD_PULSE_Msk) ; SMC->SMC_CS_NUMBER[2].SMC_CYCLE = 0 | ((22 << 0) & SMC_CYCLE_NWE_CYCLE_Msk) | ((22 << 16) & SMC_CYCLE_NRD_CYCLE_Msk) ; mode = SMC->SMC_CS_NUMBER[2].SMC_MODE; SMC->SMC_CS_NUMBER[2].SMC_MODE = (mode & ~(SMC_MODE_DBW | SMC_MODE_READ_MODE | SMC_MODE_WRITE_MODE)) | (SMC_MODE_READ_MODE) | (SMC_MODE_WRITE_MODE) | (SMC_MODE_DBW) ; delay(5); /* Delay 50 ms */ /* Start internal OSC */ wr_reg(0x19, 0x49); /* OSCADJ=10 0000, OSD_EN=1 // 60Hz */ wr_reg(0x93, 0x0C); /* RADJ=1100 */ /* Power on flow */ wr_reg(0x44, 0x4D); /* VCM=100 1101 */ wr_reg(0x45, 0x11); /* VDV=1 0001 */ wr_reg(0x20, 0x40); /* BT=0100 */ wr_reg(0x1D, 0x07); /* VC1=111 */ wr_reg(0x1E, 0x00); /* VC3=000 */ wr_reg(0x1F, 0x04); /* VRH=0100 */ wr_reg(0x1C, 0x04); /* AP=100 */ wr_reg(0x1B, 0x10); /* GASENB=0, PON=1, DK=0, XDK=0, DDVDH_TRI=0, STB=0 */ delay(5); wr_reg(0x43, 0x80); /* Set VCOMG=1 */ delay(5); /* Gamma for CMO 2.8 */ wr_reg(0x46, 0x95); wr_reg(0x47, 0x51); wr_reg(0x48, 0x00); wr_reg(0x49, 0x36); wr_reg(0x4A, 0x11); wr_reg(0x4B, 0x66); wr_reg(0x4C, 0x14); wr_reg(0x4D, 0x77); wr_reg(0x4E, 0x13); wr_reg(0x4F, 0x4C); wr_reg(0x50, 0x46); wr_reg(0x51, 0x46); /* Display Setting */ wr_reg(0x01, 0x06); /* IDMON=0, INVON=1, NORON=1, PTLON=0 */ #if (LANDSCAPE == 1) wr_reg(0x16, 0x68); /* MY=0, MX=1, MV=1, BGR=1 */ #else wr_reg(0x16, 0xC8); /* MY=1, MX=1, MV=0, BGR=1 */ #endif wr_reg(0x23, 0x95); /* N_DC=1001 0101 */ wr_reg(0x24, 0x95); /* P_DC=1001 0101 */ wr_reg(0x25, 0xFF); /* I_DC=1111 1111 */ wr_reg(0x27, 0x06); /* N_BP=0000 0110 */ wr_reg(0x28, 0x06); /* N_FP=0000 0110 */ wr_reg(0x29, 0x06); /* P_BP=0000 0110 */ wr_reg(0x2A, 0x06); /* P_FP=0000 0110 */ wr_reg(0x2C, 0x06); /* I_BP=0000 0110 */ wr_reg(0x2D, 0x06); /* I_FP=0000 0110 */ wr_reg(0x3A, 0x01); /* N_RTN=0000, N_NW=001 */ wr_reg(0x3B, 0x01); /* P_RTN=0000, P_NW=001 */ wr_reg(0x3C, 0xF0); /* I_RTN=1111, I_NW=000 */ wr_reg(0x3D, 0x00); /* DIV=00 */ wr_reg(0x3E, 0x38); /* SON=38h */ wr_reg(0x40, 0x0F); /* GDON=0Fh */ wr_reg(0x41, 0xF0); /* GDOF=F0h */ /* Display ON Setting */ wr_reg(0x90, 0x7F); /* SAP=0111 1111 */ wr_reg(0x26, 0x04); /* GON=0, DTE=0, D=01 */ delay(10); wr_reg(0x26, 0x24); /* GON=1, DTE=0, D=01 */ wr_reg(0x26, 0x2C); /* GON=1, DTE=0, D=11 */ delay(10); wr_reg(0x26, 0x3C); /* GON=1, DTE=1, D=11 */ #if (LANDSCAPE == 1) #if (ROTATE180 == 0) wr_reg (0x16, 0xA8); #else wr_reg (0x16, 0x68); #endif #else #if (ROTATE180 == 0) wr_reg (0x16, 0x08); #else wr_reg (0x16, 0xC8); #endif #endif /* Display scrolling settings ----------------------------------------------*/ wr_reg(0x0E, 0x00); /* TFA MSB */ wr_reg(0x0F, 0x00); /* TFA LSB */ wr_reg(0x10, 320 >> 8); /* VSA MSB */ wr_reg(0x11, 320 & 0xFF); /* VSA LSB */ wr_reg(0x12, 0x00); /* BFA MSB */ wr_reg(0x13, 0x00); /* BFA LSB */ /* Turn backlight on with a certain backlight level */ for (i = 0; i < 25 /* level */; i++) { PIOB->PIO_SODR = (LCD_BACKLIGHT); PIOB->PIO_SODR = (LCD_BACKLIGHT); PIOB->PIO_SODR = (LCD_BACKLIGHT); PIOB->PIO_CODR = (LCD_BACKLIGHT); PIOB->PIO_CODR = (LCD_BACKLIGHT); PIOB->PIO_CODR = (LCD_BACKLIGHT); } PIOB->PIO_SODR = (LCD_BACKLIGHT); PMC->PMC_WPMR = 0x504D4301; /* Enable write protect */ }
void GLCD_init (void) { #ifndef ILI9341 static unsigned short DriverCode; #endif // Hardware interface // nCS PC6 // RS PD13 // nWR PD14 // nRD PD15 // DATA[15:0] PE[15:0] /* Enable clock for GPIOA,B,C,D,E AFIO and SPI3. */ RCC->APB2ENR |= 0x0000007D; /* PE output set to high. */ GPIOE->CRL = 0x33333333; // output push-pull GPIOE->CRH = 0x33333333; // output push-pull GPIOC->CRL &= 0xf0ffffff; // PC6 output push-pull 50MHz GPIOC->CRL |= 0x03000000; GPIOD->CRH &= 0x000fffff; //PD13,14,15 output push-pull 50MHz GPIOD->CRH |= 0x33300000; GPIOC->BSRR = 0x00000040; //cs = 1; GPIOD->BSRR = 0x0000E000; //rs,wr,rd = 1; delay(10); /* Delay 50 ms */ #ifdef ILI9341 ili9341_read_id(); wr_cmd(0x11); delay(20); wr_cmd(0xD0); wr_dat(0x07); wr_dat(0x41); wr_dat(0x1F); wr_cmd(0xD1); wr_dat(0x00); wr_dat(0x2C); wr_dat(0x1A); wr_cmd(0xD2); wr_dat(0x01); wr_dat(0x11); wr_cmd(0xC0); wr_dat(0x00); wr_dat(0x3B); wr_dat(0x00); wr_dat(0x02); wr_dat(0x11); wr_cmd(0xC5); wr_dat(0x02); wr_cmd(0xC8); wr_dat(0x07); wr_dat(0x07); wr_dat(0x07); wr_dat(0x50); wr_dat(0x08); wr_dat(0x00); wr_dat(0x07); wr_dat(0x07); wr_dat(0x07); wr_dat(0x05); wr_dat(0x02); wr_dat(0x06); wr_cmd(0x36); // MADCTRL (Memory Access Control) wr_dat(0xE8); //0x4B, 0x48 wr_cmd(0x3A); wr_dat(0x55); wr_cmd(0xF0); wr_dat(0x01); wr_cmd(0xF3); wr_dat(0x40); wr_dat(0x0A); wr_cmd(0x2A); wr_dat(0x00); wr_dat(0x00); wr_dat(0x01); wr_dat(0x3F); wr_cmd(0x2B); wr_dat(0x00); wr_dat(0x00); wr_dat(0x01); wr_dat(0xDF); delay(120); wr_cmd(0x29); wr_cmd(0x2C); delay(5); #else /* not ILI9341*/ DriverCode = rd_reg(0x00); //printf ("GLCD driver code=%x\n", DriverCode); if(DriverCode == 0x9320) { /* Start Initial Sequence --------------------------------------------------*/ wr_reg(0xE5, 0x8000); /* Set the internal vcore voltage */ wr_reg(0x00, 0x0001); /* Start internal OSC */ wr_reg(0x01, 0x0100); /* Set SS and SM bit */ wr_reg(0x02, 0x0700); /* Set 1 line inversion */ wr_reg(0x03, 0x1030); /* Set GRAM write direction and BGR=1 */ wr_reg(0x04, 0x0000); /* Resize register */ wr_reg(0x08, 0x0202); /* 2 lines each, back and front porch */ wr_reg(0x09, 0x0000); /* Set non-disp area refresh cyc ISC */ wr_reg(0x0A, 0x0000); /* FMARK function */ wr_reg(0x0C, 0x0000); /* RGB interface setting */ wr_reg(0x0D, 0x0000); /* Frame marker Position */ wr_reg(0x0F, 0x0000); /* RGB interface polarity */ /* Power On sequence -------------------------------------------------------*/ wr_reg(0x10, 0x0000); /* Reset Power Control 1 */ wr_reg(0x11, 0x0000); /* Reset Power Control 2 */ wr_reg(0x12, 0x0000); /* Reset Power Control 3 */ wr_reg(0x13, 0x0000); /* Reset Power Control 4 */ delay(20); /* Discharge cap power voltage (200ms)*/ wr_reg(0x10, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ wr_reg(0x11, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */ delay(5); /* Delay 50 ms */ wr_reg(0x12, 0x0139); /* VREG1OUT voltage */ delay(5); /* Delay 50 ms */ wr_reg(0x13, 0x1D00); /* VDV[4:0] for VCOM amplitude */ wr_reg(0x29, 0x0013); /* VCM[4:0] for VCOMH */ delay(5); /* Delay 50 ms */ wr_reg(0x20, 0x0000); /* GRAM horizontal Address */ wr_reg(0x21, 0x0000); /* GRAM Vertical Address */ /* Adjust the Gamma Curve --------------------------------------------------*/ wr_reg(0x30, 0x0006); wr_reg(0x31, 0x0101); wr_reg(0x32, 0x0003); wr_reg(0x35, 0x0106); wr_reg(0x36, 0x0B02); wr_reg(0x37, 0x0302); wr_reg(0x38, 0x0707); wr_reg(0x39, 0x0007); wr_reg(0x3C, 0x0600); wr_reg(0x3D, 0x020B); /* Set GRAM area -----------------------------------------------------------*/ wr_reg(0x50, 0x0000); /* Horizontal GRAM Start Address */ wr_reg(0x51, (HEIGHT-1)); /* Horizontal GRAM End Address */ wr_reg(0x52, 0x0000); /* Vertical GRAM Start Address */ wr_reg(0x53, (WIDTH-1)); /* Vertical GRAM End Address */ wr_reg(0x60, 0x2700); /* Gate Scan Line */ wr_reg(0x61, 0x0001); /* NDL,VLE, REV */ wr_reg(0x6A, 0x0000); /* Set scrolling line */ /* Partial Display Control -------------------------------------------------*/ wr_reg(0x80, 0x0000); wr_reg(0x81, 0x0000); wr_reg(0x82, 0x0000); wr_reg(0x83, 0x0000); wr_reg(0x84, 0x0000); wr_reg(0x85, 0x0000); /* Panel Control -----------------------------------------------------------*/ wr_reg(0x90, 0x0010); wr_reg(0x92, 0x0000); wr_reg(0x93, 0x0003); wr_reg(0x95, 0x0110); wr_reg(0x97, 0x0000); wr_reg(0x98, 0x0000); /* Set GRAM write direction and BGR = 1 I/D=10 (Horizontal : increment, Vertical : increment) AM=1 (address is updated in vertical writing direction) */ wr_reg(0x03, 0x1038); wr_reg(0x07, 0x0173); /* 262K color and display ON */ } else if(DriverCode == 0x7783) { // Start Initial Sequence wr_reg(0x00FF,0x0001); wr_reg(0x00F3,0x0008); wr_reg(0x0001,0x0100); wr_reg(0x0002,0x0700); wr_reg(0x0003,0x1030); //0x1030 wr_reg(0x0008,0x0302); wr_reg(0x0008,0x0207); // Power On sequence wr_reg(0x0009,0x0000); wr_reg(0x000A,0x0000); wr_reg(0x0010,0x0000); //0x0790 wr_reg(0x0011,0x0005); wr_reg(0x0012,0x0000); wr_reg(0x0013,0x0000); delay(100); wr_reg(0x0010,0x12B0); delay(100);; wr_reg(0x0011,0x0007); delay(100); wr_reg(0x0012,0x008B); delay(100); wr_reg(0x0013,0x1700); delay(100); wr_reg(0x0029,0x0022); // void Gamma_Set(void) wr_reg(0x0030,0x0000); wr_reg(0x0031,0x0707); wr_reg(0x0032,0x0505); wr_reg(0x0035,0x0107); wr_reg(0x0036,0x0008); wr_reg(0x0037,0x0000); wr_reg(0x0038,0x0202); wr_reg(0x0039,0x0106); wr_reg(0x003C,0x0202); wr_reg(0x003D,0x0408); delay(100); // Set GRAM area wr_reg(0x0050,0x0000); wr_reg(0x0051,0x00EF); wr_reg(0x0052,0x0000); wr_reg(0x0053,0x013F); wr_reg(0x0060,0xA700); wr_reg(0x0061,0x0001); wr_reg(0x0090,0x0033); wr_reg(0x002B,0x000B); /* Set GRAM write direction and BGR = 1 I/D=10 (Horizontal : increment, Vertical : increment) AM=1 (address is updated in vertical writing direction) */ wr_reg(0x03, 0x1038); wr_reg(0x0007,0x0133); } else { if (DriverCode == 0x9325) { //printf ("Init ILI9325 LCD module\n"); wr_reg(0x00e7,0x0010); wr_reg(0x0000,0x0001);//?????? wr_reg(0x0001,0x0100); wr_reg(0x0002,0x0700);//???? #define ID_AM 011 #if ID_AM==000 wr_reg(0x0003,0x1000); // TFM=0,TRI=0,SWAP=1,16 bits system interface swap RGB to BRG,ORG HWM 0 #elif ID_AM==001 wr_reg(0x0003,0x1008); #elif ID_AM==010 wr_reg(0x0003,0x1010); #elif ID_AM==011 wr_reg(0x0003,0x1018); #elif ID_AM==100 wr_reg(0x0003,0x1020); #elif ID_AM==101 wr_reg(0x0003,0x1028); #elif ID_AM==110 wr_reg(0x0003,0x1030); #elif ID_AM==111 wr_reg(0x0003,0x1038); #endif wr_reg(0x0004,0x0000); wr_reg(0x0008,0x0207); wr_reg(0x0009,0x0000); wr_reg(0x000a,0x0000);//display setting wr_reg(0x000c,0x0001);//display setting wr_reg(0x000d,0x0000);//0f3c wr_reg(0x000f,0x0000); wr_reg(0x0010,0x0000); wr_reg(0x0011,0x0007); wr_reg(0x0012,0x0000); wr_reg(0x0013,0x0000); delay(5); wr_reg(0x0010,0x1590); wr_reg(0x0011,0x0227); delay(5); wr_reg(0x0012,0x009c); delay(5); wr_reg(0x0013,0x1900); wr_reg(0x0029,0x0023); wr_reg(0x002b,0x000e); delay(5); wr_reg(0x0020,0x0000); wr_reg(0x0021,0x013f); delay(5); wr_reg(0x0030,0x0007); wr_reg(0x0031,0x0707); wr_reg(0x0032,0x0006); wr_reg(0x0035,0x0704); wr_reg(0x0036,0x1f04); wr_reg(0x0037,0x0004); wr_reg(0x0038,0x0000); wr_reg(0x0039,0x0706); wr_reg(0x003c,0x0701); wr_reg(0x003d,0x000f); delay(5); wr_reg(0x0050,0x0000); wr_reg(0x0051,0x00ef); wr_reg(0x0052,0x0000); wr_reg(0x0053,0x013f); wr_reg(0x0060,0xa700); wr_reg(0x0061,0x0001); wr_reg(0x006a,0x0000); wr_reg(0x0080,0x0000); wr_reg(0x0081,0x0000); wr_reg(0x0082,0x0000); wr_reg(0x0083,0x0000); wr_reg(0x0084,0x0000); wr_reg(0x0085,0x0000); wr_reg(0x0090,0x0010); wr_reg(0x0092,0x0000); wr_reg(0x0093,0x0003); wr_reg(0x0095,0x0110); wr_reg(0x0097,0x0000); wr_reg(0x0098,0x0000); wr_reg(0x0007,0x0133); wr_reg(0x0020,0x0000); wr_reg(0x0021,0x013f); } } #endif /* ILI9341 */ }
void GLCD_Init (void) { uint32_t i; /* Connect base clock */ LPC_CGU->BASE_SSP0_CLK = (1 << 11) | (0x09 << 24) ; /* PLL1 is SSP0 clock source */ LPC_CGU->BASE_LCD_CLK = (1 << 11) | (0x10 << 24) ; /* IDIVE is clock source */ /* Enable GPIO register interface clock */ LPC_CCU1->CLK_M3_GPIO_CFG = CCU_CLK_CFG_AUTO | CCU_CLK_CFG_RUN; while (!(LPC_CCU1->CLK_M3_GPIO_STAT & CCU_CLK_STAT_RUN)); /* Enable SSP0 register interface clock */ LPC_CCU1->CLK_M3_SSP0_CFG = CCU_CLK_CFG_AUTO | CCU_CLK_CFG_RUN; while (!(LPC_CCU1->CLK_M3_SSP0_STAT & CCU_CLK_STAT_RUN)); /* Enable LCD clock */ LPC_CCU1->CLK_M3_LCD_CFG = CCU_CLK_CFG_AUTO | CCU_CLK_CFG_RUN; while (!(LPC_CCU1->CLK_M3_LCD_STAT & CCU_CLK_STAT_RUN)); /* Configure SSP0 peripheral -----------------------------------------------*/ LPC_SSP0->CR0 = (1<<7)|(1<<6)|0x7; /* 8-bit transfer CPHA = 1, CPOL = 1 */ LPC_SSP0->CPSR = 0x08; /* SPI Clock = PCLK / (8 + 1) */ LPC_SSP0->CR1 = (0<<2)|(1<<1); /* Enable SSP controller, master mode */ /* Configure SPI peripheral pins -------------------------------------------*/ LPC_SCU->SFSPF_0 = SPI_PIN_SET | 0; /* PF_0: SCL (SSP0 pin) */ LPC_SCU->SFSPF_1 = SPI_PIN_SET | 4; /* PF_1: CS (GPIO7[16] pin) */ LPC_SCU->SFSPF_2 = SPI_PIN_SET | 2; /* PF_2: SDO (SSP0 pin) */ LPC_SCU->SFSPF_3 = SPI_PIN_SET | 2; /* PF_3: SDI (SSP0 pin) */ LPC_GPIO_PORT->DIR[7] |= PIN_CS; /* Chip select pin is GPIO output */ /* Configure LCD controller pins -------------------------------------------*/ LPC_SCU->SFSP4_1 = LCD_PIN_SET | 5; /* P4_1: LCD_VD19 */ LPC_SCU->SFSP4_2 = LCD_PIN_SET | 2; /* P4_2: LCD_VD3 */ LPC_SCU->SFSP4_5 = LCD_PIN_SET | 2; /* P4_5: LCD_VSYNC */ LPC_SCU->SFSP4_6 = LCD_PIN_SET | 2; /* P4_6: LCD_EN */ LPC_SCU->SFSP4_7 = LCD_PIN_SET | 0; /* P4_7: LCD_DOTCLK */ LPC_SCU->SFSP4_9 = LCD_PIN_SET | 2; /* P4_9: LCD_VD11 */ LPC_SCU->SFSP4_10 = LCD_PIN_SET | 2; /* P4_10: LCD_VD10 */ LPC_SCU->SFSP7_0 = LCD_NPR_SET | 0; /* P7_0: LCD_BL_EN */ LPC_SCU->SFSP7_6 = LCD_PIN_SET | 3; /* P7_6: LCD_HSYNC */ LPC_SCU->SFSP8_3 = LCD_PIN_SET | 3; /* P8_3: LCD_VD12 */ LPC_SCU->SFSP8_4 = LCD_PIN_SET | 3; /* P8_4: LCD_VD7 */ LPC_SCU->SFSP8_5 = LCD_PIN_SET | 3; /* P8_5: LCD_VD6 */ LPC_SCU->SFSP8_6 = LCD_PIN_SET | 3; /* P8_6: LCD_VD5 */ LPC_SCU->SFSP8_7 = LCD_PIN_SET | 3; /* P8_7: LCD_VD4 */ LPC_SCU->SFSPB_0 = LCD_PIN_SET | 2; /* PB_0: LCD_VD23 */ LPC_SCU->SFSPB_1 = LCD_PIN_SET | 2; /* PB_1: LCD_VD22 */ LPC_SCU->SFSPB_2 = LCD_PIN_SET | 2; /* PB_2: LCD_VD21 */ LPC_SCU->SFSPB_3 = LCD_PIN_SET | 2; /* PB_3: LCD_VD20 */ LPC_SCU->SFSPB_4 = LCD_PIN_SET | 2; /* PB_4: LCD_VD15 */ LPC_SCU->SFSPB_5 = LCD_PIN_SET | 2; /* PB_5: LCD_VD14 */ LPC_SCU->SFSPB_6 = LCD_PIN_SET | 2; /* PB_6: LCD_VD13 */ /* LCD with HX8347-D LCD Controller */ /* Driving ability settings ------------------------------------------------*/ wr_reg(0xEA, 0x00); /* Power control internal used (1) */ wr_reg(0xEB, 0x20); /* Power control internal used (2) */ wr_reg(0xEC, 0x0C); /* Source control internal used (1) */ wr_reg(0xED, 0xC7); /* Source control internal used (2) */ wr_reg(0xE8, 0x38); /* Source output period Normal mode */ wr_reg(0xE9, 0x10); /* Source output period Idle mode */ wr_reg(0xF1, 0x01); /* RGB 18-bit interface ;0x0110 */ wr_reg(0xF2, 0x10); /* Adjust the Gamma Curve --------------------------------------------------*/ wr_reg(0x40, 0x01); wr_reg(0x41, 0x00); wr_reg(0x42, 0x00); wr_reg(0x43, 0x10); wr_reg(0x44, 0x0E); wr_reg(0x45, 0x24); wr_reg(0x46, 0x04); wr_reg(0x47, 0x50); wr_reg(0x48, 0x02); wr_reg(0x49, 0x13); wr_reg(0x4A, 0x19); wr_reg(0x4B, 0x19); wr_reg(0x4C, 0x16); wr_reg(0x50, 0x1B); wr_reg(0x51, 0x31); wr_reg(0x52, 0x2F); wr_reg(0x53, 0x3F); wr_reg(0x54, 0x3F); wr_reg(0x55, 0x3E); wr_reg(0x56, 0x2F); wr_reg(0x57, 0x7B); wr_reg(0x58, 0x09); wr_reg(0x59, 0x06); wr_reg(0x5A, 0x06); wr_reg(0x5B, 0x0C); wr_reg(0x5C, 0x1D); wr_reg(0x5D, 0xCC); /* Power voltage setting ---------------------------------------------------*/ wr_reg(0x1B, 0x1B); wr_reg(0x1A, 0x01); wr_reg(0x24, 0x2F); wr_reg(0x25, 0x57); wr_reg(0x23, 0x88); /* Power on setting --------------------------------------------------------*/ wr_reg(0x18, 0x36); /* Internal oscillator frequency adj */ wr_reg(0x19, 0x01); /* Enable internal oscillator */ wr_reg(0x01, 0x00); /* Normal mode, no scrool */ wr_reg(0x1F, 0x88); /* Power control 6 - DDVDH Off */ delay(20); wr_reg(0x1F, 0x82); /* Power control 6 - Step-up: 3 x VCI */ delay(5); wr_reg(0x1F, 0x92); /* Power control 6 - Step-up: On */ delay(5); wr_reg(0x1F, 0xD2); /* Power control 6 - VCOML active */ delay(5); /* Color selection ---------------------------------------------------------*/ wr_reg(0x17, 0x55); /* RGB, System interface: 16 Bit/Pixel*/ wr_reg(0x00, 0x00); /* Scrolling off, no standby */ /* Interface config --------------------------------------------------------*/ wr_reg(0x2F, 0x11); /* LCD Drive: 1-line inversion */ wr_reg(0x31, 0x02); /* Value for SPI: 0x02, RBG: 0x02 */ wr_reg(0x32, 0x00); /* DPL=0, HSPL=0, VSPL=0, EPL=0 */ /* Display on setting ------------------------------------------------------*/ wr_reg(0x28, 0x38); /* PT(0,0) active, VGL/VGL */ delay(20); wr_reg(0x28, 0x3C); /* Display active, VGL/VGL */ /* MY MX MV ML BGR */ #if (LANDSCAPE == 1) #if (ROTATE180 == 0) wr_reg (0x16, ((1 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (0 << 3))); #else wr_reg (0x16, ((0 << 7) | (1 << 6) | (0 << 5) | (1 << 4) | (0 << 3))); #endif #else /* Portrait */ #if (ROTATE180 == 0) wr_reg (0x16, ((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (0 << 3))); #else wr_reg (0x16, ((1 << 7) | (1 << 6) | (0 << 5) | (0 << 4) | (0 << 3))); #endif #endif /* Display scrolling settings ----------------------------------------------*/ wr_reg(0x0E, 0x00); /* TFA MSB */ wr_reg(0x0F, 0x00); /* TFA LSB */ wr_reg(0x10, 320 >> 8); /* VSA MSB */ wr_reg(0x11, 320 & 0xFF); /* VSA LSB */ wr_reg(0x12, 0x00); /* BFA MSB */ wr_reg(0x13, 0x00); /* BFA LSB */ /* Configure LCD controller ------------------------------------------------*/ LPC_RGU->RESET_CTRL0 = (1U << 16); while ((LPC_RGU->RESET_ACTIVE_STATUS0 & (1U << 16)) == 0); LPC_LCD->CTRL &= ~(1 << 0); /* Disable LCD */ LPC_LCD->INTMSK = 0; /* Disable all interrupts */ LPC_LCD->UPBASE = SDRAM_BASE_ADDR; LPC_LCD->TIMH = (7 << 24) | /* Horizontal back porch */ (3 << 16) | /* Horizontal front porch */ (3 << 8) | /* Horizontal sync pulse width */ (14 << 2) ; /* Pixels-per-line */ LPC_LCD->TIMV = (3 << 24) | /* Vertical back porch */ (2 << 16) | /* Vertical front porch */ (3 << 10) | /* Vertical sync pulse width */ (319 << 0) ; /* Lines per panel */ LPC_LCD->POL = (1 << 26) | /* Bypass pixel clock divider */ (239 << 16) | /* Clocks per line: num of LCDCLKs */ (1 << 13) | /* Invert panel clock */ (1 << 12) | /* Invert HSYNC */ (1 << 11) ; /* Invert VSYNC */ LPC_LCD->LE = (1 << 16) | /* LCDLE Enabled: 1, Disabled: 0 */ (9 << 0) ; /* Line-end delay: LCDCLK clocks - 1 */ LPC_LCD->CTRL = (1 << 11) | /* LCD Power Enable */ (1 << 5) | /* 0 = STN display, 1: TFT display */ (6 << 1) ; /* Bits per pixel: 16bpp (5:6:5) */ for (i = 0; i < 256; i++) { LPC_LCD->PAL[i] = 0; /* Clear palette */ } LPC_LCD->CTRL |= (1 << 0); /* LCD enable */ /* Turn on backlight -------------------------------------------------------*/ LPC_GPIO_PORT->DIR[3] |= (1 << 8); LPC_GPIO_PORT->SET[3] = (1 << 8); }