void
C64::saveToBuffer(uint8_t **buffer)
{
uint8_t *old = *buffer;
debug(3, "Saving internal state...\n");
// Save state of this component
write8(buffer, warp);
write8(buffer, alwaysWarp);
write8(buffer, warpLoad);
write64(buffer, cycles);
write32(buffer, (uint32_t)frame);
write16(buffer, rasterline);
write32(buffer, (uint32_t)rasterlineCycle);
write64(buffer, nanoTargetTime);
// Save state of sub components
cpu->saveToBuffer(buffer);
vic->saveToBuffer(buffer);
sid->saveToBuffer(buffer);
cia1->saveToBuffer(buffer);
cia2->saveToBuffer(buffer);
mem->saveToBuffer(buffer);
keyboard->saveToBuffer(buffer);
joystick1->saveToBuffer(buffer);
joystick2->saveToBuffer(buffer);
iec->saveToBuffer(buffer);
expansionport->saveToBuffer(buffer);
floppy->saveToBuffer(buffer);
debug(3, " C64 state saved (%d bytes)\n", *buffer - old);
assert(*buffer - old == stateSize());
}
/*-----------------------------------------------------------------------------
* dt_out_front_ex
*---------------------------------------------------------------------------*/
void
dt_out_front_ex(BUFFER_CB *buf, uint32_t dest_spu, SPU_ADDRESS dest_buf_data,
uint32_t num_bytes)
{
OUT_DTCB out_dtcb;
#if CHECK
// Validate alignment.
pcheck(((dest_buf_data & CACHE_MASK) == 0) && (num_bytes != 0));
// Debug head pointer should be synchronized.
assert(buf->ihead == buf->head);
// Make sure front of buffer is free. out-out is disallowed.
check((buf->front_action == BUFFER_ACTION_NONE) &&
(buf->back_action != BUFFER_ACTION_OUT));
// Make sure enough data is available.
check(((buf->tail - buf->head) & buf->mask) >= num_bytes);
#endif
// Set up source buffer's head/tail pointers for region to be transferred.
out_dtcb.head = buf->head;
out_dtcb.tail = (buf->head + num_bytes) & buf->mask;
buf->head = out_dtcb.tail;
IF_CHECK(buf->ihead = buf->head);
// Write transfer info to destination SPU.
write64((uint64_t *)buf_get_dt_field_addr(spu_addr(dest_spu, dest_buf_data),
back_in_dtcb),
out_dtcb.data);
}
static bool write64A( u32 Offset, u64 Value, u64 CurrentValue )
{
if( read64(Offset) != CurrentValue )
return false;
write64( Offset, Value );
return true;
}
QByteArray Mda::toByteArray64() const
{
QString path = CacheManager::globalInstance()->makeLocalFile("", CacheManager::ShortTerm);
write64(path);
QByteArray ret = MLUtil::readByteArray(path);
QFile::remove(path);
return ret;
}
/*-----------------------------------------------------------------------------
* dt_in_back
*---------------------------------------------------------------------------*/
void
dt_in_back(BUFFER_CB *buf, uint32_t src_spu, SPU_ADDRESS src_buf_data,
uint32_t num_bytes, uint32_t spu_cmd_id, uint32_t tag)
{
OUT_DTCB out_dtcb;
PPU_DT_PARAMS *cmd;
#if CHECK
// Validate buffer alignment.
pcheck(((src_buf_data & CACHE_MASK) == 0) && (num_bytes != 0));
// Debug tail pointer should be synchronized.
assert(buf->otail == buf->tail);
// Make sure back of buffer is free. *-in is allowed.
check(buf->back_action == BUFFER_ACTION_NONE);
buf->back_action = BUFFER_ACTION_IN;
#if !DT_ALLOW_UNALIGNED
// Make sure data is aligned on qword boundary.
pcheck((num_bytes & QWORD_MASK) == 0);
check((buf->tail & QWORD_MASK) == 0);
#endif
// Make sure enough space is available. head and tail must be off by at least
// 1 and cannot be non-zero offsets in the same qword.
check(((buf->head - (buf->head & QWORD_MASK ? : 1) - buf->tail) &
buf->mask) >= num_bytes);
#endif
// Set up description of region in destination buffer that source SPU will
// write to. Data/space in source/destination buffers must have same offset
// within cache line (128 bytes) - destination buffer does not automatically
// adjust pointers if empty.
out_dtcb.head = buf->tail;
out_dtcb.tail = (buf->tail + num_bytes) & buf->mask;
// Reserve space for data to be transferred.
IF_CHECK(buf->otail = out_dtcb.tail);
// Set data transfer to wait on the SPU command ID. This must be done before
// writing transfer info to SPU.
cmd = ppu_dt_wait_spu(src_spu, spu_cmd_id, tag);
cmd->type = PPU_CMD_DT_IN_BACK;
cmd->buf = buf;
cmd->num_bytes = num_bytes;
// Write transfer info to source SPU.
write64((uint64_t *)buf_get_dt_field_addr(spu_addr(src_spu, src_buf_data),
front_in_dtcb),
out_dtcb.data);
}
s32 sys_spu_thread_write_ls(u32 id, u32 address, u64 value, u32 type)
{
sys_spu.Log("sys_spu_thread_write_ls(id=0x%x, address=0x%x, value=0x%llx, type=%d)", id, address, value, type);
LV2_LOCK;
const auto thread = Emu.GetIdManager().get<SPUThread>(id);
if (!thread)
{
return CELL_ESRCH;
}
if (address >= 0x40000 || address + type > 0x40000 || address % type) // check range and alignment
{
return CELL_EINVAL;
}
const auto group = thread->tg.lock();
if (!group)
{
throw EXCEPTION("Invalid SPU thread group");
}
if ((group->state < SPU_THREAD_GROUP_STATUS_WAITING) || (group->state > SPU_THREAD_GROUP_STATUS_RUNNING))
{
return CELL_ESTAT;
}
switch (type)
{
case 1:
thread->write8(address, (u8)value);
break;
case 2:
thread->write16(address, (u16)value);
break;
case 4:
thread->write32(address, (u32)value);
break;
case 8:
thread->write64(address, value);
break;
default:
return CELL_EINVAL;
}
return CELL_OK;
}
void BufWriter::writeDwarfPointer(DwarfPointer ptr)
{
switch (ptr.encoding & 0xf)
{
case 0x01: // uleb128
writeULEB128(ptr.udata8);
break;
case 0x02: // udata2
write16(ptr.udata2);
break;
case 0x03: // udata4
write32(ptr.udata4);
break;
case 0x04: // udata8
write64(ptr.udata8);
break;
case (0x01|0x08): // sleb128
writeLEB128(ptr.sdata8);
break;
case (0x02|0x08): // sdata2
write16S(ptr.sdata2);
break;
case (0x03|0x08): // sdata4
write32S(ptr.sdata4);
break;
case (0x04|0x08): // sdata8
write64S(ptr.sdata8);
break;
case 0: // absptr
{
if (sizeof(void*) == 4)
write32(ptr.udata4);
else
write64(ptr.udata8);
}
}
}
void writeword(enum arch arch, uint64_t data, void *iptr, enum endianness endianness)
{
switch (arch_to_wordsize(arch)) {
case WS_32BIT:
write32 (data, iptr, endianness);
break;
case WS_64BIT:
write64 (data, iptr, endianness);
break;
case WS_UNKNOWN:
default:
fprintf (stderr, "writeword: Unknown architecture");
exit (1);
}
}
void
VirtualComponent::saveToBuffer(uint8_t **buffer)
{
uint8_t *old = *buffer;
debug(3, " Saving internal state (%d bytes) ...\n", VirtualComponent::stateSize());
// Save internal state of sub components
if (subComponents != NULL) {
for (unsigned i = 0; subComponents[i] != NULL; i++)
subComponents[i]->saveToBuffer(buffer);
}
// Save own internal state
void *data; size_t size; int flags;
for (unsigned i = 0; snapshotItems != NULL && snapshotItems[i].data != NULL; i++) {
data = snapshotItems[i].data;
flags = snapshotItems[i].flags & 0x0F;
size = snapshotItems[i].size;
if (flags == 0) { // Auto detect size
switch (snapshotItems[i].size) {
case 1: write8(buffer, *(uint8_t *)data); break;
case 2: write16(buffer, *(uint16_t *)data); break;
case 4: write32(buffer, *(uint32_t *)data); break;
case 8: write64(buffer, *(uint64_t *)data); break;
default: writeBlock(buffer, (uint8_t *)data, size);
}
} else { // Format is specified manually
switch (flags) {
case BYTE_FORMAT: writeBlock(buffer, (uint8_t *)data, size); break;
case WORD_FORMAT: writeBlock16(buffer, (uint16_t *)data, size); break;
case DOUBLE_WORD_FORMAT: writeBlock32(buffer, (uint32_t *)data, size); break;
case QUAD_WORD_FORMAT: writeBlock64(buffer, (uint64_t *)data, size); break;
default: assert(0);
}
}
}
if (*buffer - old != VirtualComponent::stateSize()) {
panic("saveToBuffer: Snapshot size is wrong.");
assert(false);
}
}
acpi_status
acpi_os_write_memory(acpi_physical_address phys_addr, u64 value, u32 width)
{
void __iomem *virt_addr;
unsigned int size = width / 8;
bool unmap = false;
rcu_read_lock();
virt_addr = acpi_map_vaddr_lookup(phys_addr, size);
if (!virt_addr) {
rcu_read_unlock();
virt_addr = acpi_os_ioremap(phys_addr, size);
if (!virt_addr)
return AE_BAD_ADDRESS;
unmap = true;
}
switch (width) {
case 8:
writeb(value, virt_addr);
break;
case 16:
writew(value, virt_addr);
break;
case 32:
writel(value, virt_addr);
break;
case 64:
write64(value, virt_addr);
break;
default:
BUG();
}
if (unmap)
iounmap(virt_addr);
else
rcu_read_unlock();
return AE_OK;
}
void testNotSmallPageAligned64RW(result_t *result, char abort, char quiet){
int fails = 0;
int testNr = 0;
for(testNr=0; testNr<(SMALL_PAGE_SIZE / 8); testNr++){
write64(S_SANDBOXW + testNr * 8, testNr, 1);
if(read8(S_SANDBOXR + testNr * 8, testNr, 0, 1)){
fails++;
write8(S_SANDBOXW + testNr * 8, testNr, quiet);
read8(S_SANDBOXR + testNr * 8, testNr, abort, quiet);
}
if(fails >= 5){
printString("Ending test prematurely due to too many failures\n", quiet);
break;
}
}
result_t localResult;
localResult.nrFailed = fails;
localResult.nrTests = testNr + 1;
addResults(result, &localResult);
}
int writetaddr(struct GlobalVars *gv,void *p,lword d)
{
bool be = fff[gv->dest_format]->endianess == _BIG_ENDIAN_;
switch (fff[gv->dest_format]->addr_bits) {
case 16:
write16(be,p,(uint16_t)d);
return 2;
case 32:
write32(be,p,(uint32_t)d);
return 4;
case 64:
write64(be,p,(uint64_t)d);
return 8;
default:
ierror("writetaddr(): target address has %d bits",
(int)fff[gv->dest_format]->addr_bits);
break;
}
return 0;
}
/*-----------------------------------------------------------------------------
* dt_out_front
*---------------------------------------------------------------------------*/
void
dt_out_front(BUFFER_CB *buf, uint32_t dest_spu, SPU_ADDRESS dest_buf_data,
uint32_t num_bytes, uint32_t spu_cmd_id, uint32_t tag)
{
OUT_DTCB out_dtcb;
PPU_DT_PARAMS *cmd;
#if CHECK
// Validate alignment.
pcheck(((dest_buf_data & CACHE_MASK) == 0) && (num_bytes != 0));
// Debug head pointer should be synchronized.
assert(buf->ihead == buf->head);
// Make sure front of buffer is free. out-out is disallowed.
check((buf->front_action == BUFFER_ACTION_NONE) &&
(buf->back_action != BUFFER_ACTION_OUT));
buf->front_action = BUFFER_ACTION_OUT;
// Make sure enough data is available.
check(((buf->tail - buf->head) & buf->mask) >= num_bytes);
#endif
// Set up source buffer's head/tail pointers for region to be transferred.
out_dtcb.head = buf->head;
out_dtcb.tail = (buf->head + num_bytes) & buf->mask;
IF_CHECK(buf->ihead = out_dtcb.tail);
// Set data transfer to wait on the SPU command ID. This must be done before
// writing transfer info to SPU.
cmd = ppu_dt_wait_spu(dest_spu, spu_cmd_id, tag);
cmd->type = PPU_CMD_DT_OUT_FRONT;
cmd->buf = buf;
cmd->num_bytes = num_bytes;
// Write transfer info to destination SPU.
write64((uint64_t *)buf_get_dt_field_addr(spu_addr(dest_spu, dest_buf_data),
back_in_dtcb),
out_dtcb.data);
}
void PortableFile::write_double(double value)
{
uint64 *u64 = (uint64 *)&value;
write64(*u64);
}
void
CPU::saveToBuffer(uint8_t **buffer)
{
uint8_t *old = *buffer;
write8(buffer, (uint8_t)chipModel);
// Registers and flags
write8(buffer, A);
write8(buffer, X);
write8(buffer, Y);
write16(buffer, PC);
write16(buffer, PC_at_cycle_0);
write8(buffer, SP);
write8(buffer, N);
write8(buffer, V);
write8(buffer, B);
write8(buffer, D);
write8(buffer, I);
write8(buffer, Z);
write8(buffer, C);
// Internal state
write8(buffer, opcode);
write8(buffer, addr_lo);
write8(buffer, addr_hi);
write8(buffer, ptr);
write8(buffer, pc_lo);
write8(buffer, pc_hi);
write8(buffer, (uint8_t)overflow);
write8(buffer, data);
write8(buffer, port);
write8(buffer, port_direction);
write8(buffer, external_port_bits);
write8(buffer, (uint8_t)rdyLine);
write8(buffer, irqLine);
write8(buffer, nmiLine);
write8(buffer, (uint8_t)nmiEdge);
write8(buffer, (uint8_t)interruptsPending);
write64(buffer, nextPossibleIrqCycle);
write64(buffer, nextPossibleNmiCycle);
write8(buffer, (uint8_t)errorState);
for (uint16_t i = 0;; i++) {
if (callbacks[i] == NULL) {
panic("ERROR while saving state: Callback pointer not found!\n");
}
if (callbacks[i] == next) {
write16(buffer, i);
break;
}
}
for (unsigned i = 0; i < 256; i++)
write16(buffer, callStack[i]);
write8(buffer, callStackPointer);
write8(buffer, oldI);
debug(4, " CPU state saved (%d bytes)\n", *buffer - old);
assert(*buffer - old == stateSize());
}
bool Mda::write64(const QString& path) const
{
return write64(path.toLatin1().data());
}
static int amd_ntb_mw_set_trans(struct ntb_dev *ntb, int pidx, int idx,
dma_addr_t addr, resource_size_t size)
{
struct amd_ntb_dev *ndev = ntb_ndev(ntb);
unsigned long xlat_reg, limit_reg = 0;
resource_size_t mw_size;
void __iomem *mmio, *peer_mmio;
u64 base_addr, limit, reg_val;
int bar;
if (pidx != NTB_DEF_PEER_IDX)
return -EINVAL;
bar = ndev_mw_to_bar(ndev, idx);
if (bar < 0)
return bar;
mw_size = pci_resource_len(ntb->pdev, bar);
/* make sure the range fits in the usable mw size */
if (size > mw_size)
return -EINVAL;
mmio = ndev->self_mmio;
peer_mmio = ndev->peer_mmio;
base_addr = pci_resource_start(ntb->pdev, bar);
if (bar != 1) {
xlat_reg = AMD_BAR23XLAT_OFFSET + ((bar - 2) << 2);
limit_reg = AMD_BAR23LMT_OFFSET + ((bar - 2) << 2);
/* Set the limit if supported */
limit = size;
/* set and verify setting the translation address */
write64(addr, peer_mmio + xlat_reg);
reg_val = read64(peer_mmio + xlat_reg);
if (reg_val != addr) {
write64(0, peer_mmio + xlat_reg);
return -EIO;
}
/* set and verify setting the limit */
write64(limit, peer_mmio + limit_reg);
reg_val = read64(peer_mmio + limit_reg);
if (reg_val != limit) {
write64(base_addr, mmio + limit_reg);
write64(0, peer_mmio + xlat_reg);
return -EIO;
}
} else {
xlat_reg = AMD_BAR1XLAT_OFFSET;
limit_reg = AMD_BAR1LMT_OFFSET;
/* Set the limit if supported */
limit = size;
/* set and verify setting the translation address */
write64(addr, peer_mmio + xlat_reg);
reg_val = read64(peer_mmio + xlat_reg);
if (reg_val != addr) {
write64(0, peer_mmio + xlat_reg);
return -EIO;
}
/* set and verify setting the limit */
writel(limit, peer_mmio + limit_reg);
reg_val = readl(peer_mmio + limit_reg);
if (reg_val != limit) {
writel(base_addr, mmio + limit_reg);
writel(0, peer_mmio + xlat_reg);
return -EIO;
}
}
return 0;
}
/**
* Setup UART with desired BAUD rate in 8N1, no parity mode.
*
* @param bus The UART to operate on
* @param baudrate baudrate to set up
*
* @return Boolean: True on error
*/
int uart_setup(const size_t bus, int baudrate)
{
union cn81xx_uart_ctl ctl;
struct cn81xx_uart *uart = (struct cn81xx_uart *)UAAx_PF_BAR0(bus);
assert(uart);
if (!uart)
return 1;
/* 1.2.1 Initialization Sequence (Power-On/Hard/Cold Reset) */
/* 1. Wait for IOI reset (srst_n) to deassert. */
/**
* 2. Assert all resets:
* a. UAA reset: UCTL_CTL[UAA_RST] = 1
* b. UCTL reset: UCTL_CTL[UCTL_RST] = 1
*/
ctl.u = read64(&uart->uctl_ctl);
ctl.s.uctl_rst = 1;
ctl.s.uaa_rst = 1;
write64(&uart->uctl_ctl, ctl.u);
/**
* 3. Configure the HCLK:
* a. Reset the clock dividers: UCTL_CTL[H_CLKDIV_RST] = 1.
* b. Select the HCLK frequency
* i. UCTL_CTL[H_CLKDIV] = desired value,
* ii. UCTL_CTL[H_CLKDIV_EN] = 1 to enable the HCLK.
* iii. Readback UCTL_CTL to ensure the values take effect.
* c. Deassert the HCLK clock divider reset: UCTL_CTL[H_CLKDIV_RST] = 0.
*/
ctl.u = read64(&uart->uctl_ctl);
ctl.s.h_clkdiv_sel = UART_SCLK_DIV;
write64(&uart->uctl_ctl, ctl.u);
ctl.u = read64(&uart->uctl_ctl);
ctl.s.h_clk_byp_sel = 0;
write64(&uart->uctl_ctl, ctl.u);
ctl.u = read64(&uart->uctl_ctl);
ctl.s.h_clk_en = 1;
write64(&uart->uctl_ctl, ctl.u);
ctl.u = read64(&uart->uctl_ctl);
ctl.s.h_clkdiv_rst = 0;
write64(&uart->uctl_ctl, ctl.u);
/**
* 4. Wait 20 HCLK cycles from step 3 for HCLK to start and async fifo
* to properly reset.
*/
uart_wait_hclk(uart, 20 + 1);
/**
* 5. Deassert UCTL and UAHC resets:
* a. UCTL_CTL[UCTL_RST] = 0
* b. Wait 10 HCLK cycles.
* c. UCTL_CTL[UAHC_RST] = 0
* d. You will have to wait 10 HCLK cycles before accessing any
* HCLK-only registers.
*/
ctl.u = read64(&uart->uctl_ctl);
ctl.s.uctl_rst = 0;
write64(&uart->uctl_ctl, ctl.u);
uart_wait_hclk(uart, 10 + 1);
ctl.u = read64(&uart->uctl_ctl);
ctl.s.uaa_rst = 0;
write64(&uart->uctl_ctl, ctl.u);
uart_wait_hclk(uart, 10 + 1);
/**
* 6. Enable conditional SCLK of UCTL by writing
* UCTL_CTL[CSCLK_EN] = 1.
*/
ctl.u = read64(&uart->uctl_ctl);
ctl.s.csclk_en = 1;
write64(&uart->uctl_ctl, ctl.u);
/**
* Exit here if the UART is not going to be used in coreboot.
* The previous initialization steps are sufficient to make the Linux
* kernel not panic.
*/
if (!baudrate)
return 0;
/**
* 7. Initialize the integer and fractional baud rate divider registers
* UARTIBRD and UARTFBRD as follows:
* a. Baud Rate Divisor = UARTCLK/(16xBaud Rate) = BRDI + BRDF
* b. The fractional register BRDF, m is calculated as
* integer(BRDF x 64 + 0.5)
* Example calculation:
* If the required baud rate is 230400 and hclk = 4MHz then:
* Baud Rate Divisor = (4x10^6)/(16x230400) = 1.085
* This means BRDI = 1 and BRDF = 0.085.
* Therefore, fractional part, BRDF = integer((0.085x64)+0.5) = 5
* Generated baud rate divider = 1+5/64 = 1.078
*/
u64 divisor = thunderx_get_io_clock() /
(baudrate * 16 * uart_sclk_divisor(UART_SCLK_DIV) / 64);
write32(&uart->pl011.ibrd, divisor >> 6);
write32(&uart->pl011.fbrd, divisor & UART_FBRD_BAUD_DIVFRAC_MASK);
/**
* 8. Program the line control register UAA(0..1)_LCR_H and the control
* register UAA(0..1)_CR
*/
/* 8-bits, FIFO enable */
write32(&uart->pl011.lcr_h, PL011_UARTLCR_H_WLEN_8 |
PL011_UARTLCR_H_FEN);
/* RX/TX enable, UART enable */
write32(&uart->pl011.cr, PL011_UARTCR_RXE | PL011_UARTCR_TXE |
PL011_UARTCR_UARTEN);
return 0;
}
// the argument is the name of the directory or the file name
int ibis::skive::write(const char* dt) const {
if (vals.empty()) return -1;
std::string fnm;
indexFileName(fnm, dt);
if (fnm.empty()) {
return 0;
}
else if (0 != str && 0 != str->filename() &&
0 == fnm.compare(str->filename())) {
LOGGER(ibis::gVerbose > 0)
<< "Warning -- skive::write can not overwrite the index file \""
<< fnm << "\" while it is used as a read-only file map";
return 0;
}
else if (fname != 0 && *fname != 0 && 0 == fnm.compare(fname)) {
activate(); // read everything into memory
fname = 0; // break the link with the named file
}
ibis::fileManager::instance().flushFile(fnm.c_str());
int fdes = UnixOpen(fnm.c_str(), OPEN_WRITENEW, OPEN_FILEMODE);
if (fdes < 0) {
ibis::fileManager::instance().flushFile(fnm.c_str());
fdes = UnixOpen(fnm.c_str(), OPEN_WRITENEW, OPEN_FILEMODE);
if (fdes < 0) {
LOGGER(ibis::gVerbose > 0)
<< "Warning -- skive[" << col->partition()->name() << '.'
<< col->name() << "]::write failed to open \"" << fnm
<< "\" for writing";
return -2;
}
}
IBIS_BLOCK_GUARD(UnixClose, fdes);
#if defined(_WIN32) && defined(_MSC_VER)
(void)_setmode(fdes, _O_BINARY);
#endif
#ifdef FASTBIT_USE_LONG_OFFSETS
const bool useoffset64 = true;
#else
const bool useoffset64 = (getSerialSize()+8 > 0x80000000UL);
#endif
char header[] = "#IBIS\11\0\0";
header[5] = (char)ibis::index::SKIVE;
header[6] = (char)(useoffset64 ? 8 : 4);
int ierr = UnixWrite(fdes, header, 8);
if (ierr < 8) {
LOGGER(ibis::gVerbose > 0)
<< "Warning -- skive[" << col->partition()->name() << "."
<< col->name() << "]::write(" << fnm
<< ") failed to write the 8-byte header, ierr = " << ierr;
return -3;
}
if (useoffset64)
ierr = write64(fdes);
else
ierr = write32(fdes);
if (ierr >= 0) {
#if defined(FASTBIT_SYNC_WRITE)
#if _POSIX_FSYNC+0 > 0
(void) UnixFlush(fdes); // write to disk
#elif defined(_WIN32) && defined(_MSC_VER)
(void) _commit(fdes);
#endif
#endif
LOGGER(ibis::gVerbose > 3)
<< "skive[" << col->partition()->name() << "." << col->name()
<< "]::write wrote " << bits.size() << " bitmap"
<< (bits.size()>1?"s":"") << " to file " << fnm;
}
return ierr;
} // ibis::skive::write
void user_write64(struct map_info *map, __u64 d, unsigned long adr)
{
CFI_LOCK;
write64(map->map_priv_1 + adr, d);
CFI_UNLOCK;
}
