bool Cpc1475::Chk_Adr(UINT32 *d,UINT32 data)
{
if ( (*d<=0x1FFF) ) return(0); // ROM area(0000-1fff)
if ( (*d>=0x2000) && (*d<=0x27FF) ) return(0);
if ( (*d>=0x2800) && (*d<=0x2B7B) ) { pLCDC->SetDirtyBuf(*d-0x2800);pLCDC->updated = true;return(1); /* LCDC (0200x) */ }
if ( (*d>=0x2800) && (*d<=0x33FF) ) return(1);
if ( (*d>=0x3400) && (*d<=0x35FF) ) { RomBank = data &0x07; return(1); }
if ( (*d>=0x3C00) && (*d<=0x3DFF) )
{
// AddLog(LOG_MASTER,"Write Slot Register %04X=%02X",*d,mem[*d]);
// RamBank = (data == 0x04 ? 0 : 1);
// qWarning()<<"Rambank:"<<RamBank<< " ("<<data<<")";
return(1);
}
if ( (*d>=0x3E00) && (*d<=0x3FFF) )
{
BYTE KStrobe=0;
switch (data & 0x0F)
{
case 0x00: KStrobe=0x00; break;
case 0x01: KStrobe=0x01; break;
case 0x02: KStrobe=0x02; break;
case 0x03: KStrobe=0x04; break;
case 0x04: KStrobe=0x08; break;
case 0x05: KStrobe=0x10; break;
case 0x06: KStrobe=0x20; break;
case 0x07: KStrobe=0x40; break;
case 0x08: KStrobe=0x80; break;
case 0x09: KStrobe=0x00; break;
case 0x0A: KStrobe=0x00; break;
case 0x0B: KStrobe=0x00; break;
case 0x0C: KStrobe=0x00; break;
case 0x0D: KStrobe=0x00; break;
case 0x0E: KStrobe=0x00; break;
case 0x0F: KStrobe=0x7F; break;
}
pKEYB->Set_KS( KStrobe );
return(1);
}
if ( (*d>=0x2800) && (*d<=0x3FFF) ) return(1);
if ( (*d>=0x4000) && (*d<=0x7FFF) ) { *d += 0xC000 + ( RomBank * 0x4000 ); return(0); }
if ( (*d>=0x8000) && (*d<=0xFFFF) )
{
UINT32 _addr = *d &0x7FFF;
// qWarning()<<(RamBank ? "S2:" : "S1:");
writeBus(RamBank ? busS2 : busS1 ,&_addr,data);
}
return(0);
}
bool Cpc1360::Chk_Adr(UINT32 *d,UINT32 data)
{
if ( (*d<=0x1FFF) ) { return(0); } // ROM area(0000-1fff)
if ( (*d>=0x2000) && (*d<=0x27FF) ) { return(0); }
// if ( (*d>=0x2800) && (*d<=0x33FF) ) { pLCDC->SetDirtyBuf(*d-0x2800); return(1); /* LCDC (0200x) */ }
if ( ( (*d>=0x2800) && (*d<=0x287C) ) ||
( (*d>=0x2A00) && (*d<=0x2A7C) ) ||
( (*d>=0x2C00) && (*d<=0x2C7C) ) ||
( (*d>=0x2E00) && (*d<=0x2E7C) ) ||
( (*d>=0x3000) && (*d<=0x307C) )) {
if (mem[*d] != data) {
pLCDC->updated = true;
pLCDC->SetDirtyBuf(*d-0x2800);
}
return(1);
}
if ( (*d>=0x3400) && (*d<=0x35FF) ) { RomBank = data &0x07; return(1); }
if ( (*d>=0x3E00) && (*d<=0x3FFF) )
{
BYTE KStrobe=0;
switch (data & 0x0F)
{
case 0x00: KStrobe=0x00; break;
case 0x01: KStrobe=0x01; break;
case 0x02: KStrobe=0x02; break;
case 0x03: KStrobe=0x04; break;
case 0x04: KStrobe=0x08; break;
case 0x05: KStrobe=0x10; break;
case 0x06: KStrobe=0x20; break;
case 0x07: KStrobe=0x40; break;
case 0x08: KStrobe=0x80; break;
case 0x09: KStrobe=0x00; break;
case 0x0A: KStrobe=0x00; break;
case 0x0B: KStrobe=0x00; break;
case 0x0C: KStrobe=0x00; break;
case 0x0D: KStrobe=0x00; break;
case 0x0E: KStrobe=0x00; break;
case 0x0F: KStrobe=0x7F; break;
}
pKEYB->Set_KS( KStrobe );
return(1);
}
if ( (*d>=0x2800) && (*d<=0x3FFF) ) return(1);
if ( (*d>=0x4000) && (*d<=0x7FFF) ) { *d += 0xC000 + ( RomBank * 0x4000 ); return(0); }
if ( (*d>=0x8000) && (*d<=0xFFFF) )
{
UINT32 _addr = *d &0x7FFF;
// qWarning()<<(RamBank ? "S2:" : "S1:");
writeBus(RamBank ? busS2 : busS1 ,&_addr,data);
}
return(0);
}
/*
* Checks if we have an incoming request. If so, handles it.
* Returns 0 if no request was waiting. Returns 1 if request was handled.
*/
byte checkBus()
{
byte data=0;
/* No request - no action. */
if(IN_REQ == 0)
return 0;
/* Data is coming in */
if(IN_RW == RW_WRITE)
{
/* Read data */
data = readBus();
/* Acknowledge read */
LAT_AKN = 1;
TRIS_AKN = TRIS_OUT;
/* Wait for Request to drop */
/* Need a timeout here to detect Master's fault */
while(IN_REQ);
/* Drop Akn */
TRIS_AKN = TRIS_IN;
processData(data);
} else
{
/* Master requests a byte */
/* Is there data left in the buffer? */
if(txPtr >= TXBUF_LEN)
{
/* Error Condition! We have nothing to write */
}
data = txBuf[txPtr++];
/* Put data on the bus */
writeBus(data);
/* Acknowledge write */
LAT_AKN = 1;
TRIS_AKN = TRIS_OUT;
/* Wait for Request to drop */
/* Need a timeout here to detect Master's fault */
while(IN_REQ);
/* Release bus first */
freeBus();
/* Finally, release Akn */
TRIS_AKN = TRIS_IN;
}
return 1;
}
void GwfStreamWriter::writeObject(SCgObject *object)
{
Q_ASSERT(isWritingStarted);
switch (object->type())
{
case SCgNode::Type:
writeNode(object);
break;
case SCgPair::Type:
writePair(object);
break;
case SCgBus::Type:
writeBus(object);
break;
case SCgContour::Type:
writeContour(object);
break;
}
}
/* Returns BUS_ERROR or BUS_FAILURE on error */
int busWriteByte(byte data, byte req)
{
long timeout=0;
/* Set RW to write */
LAT_RW = RW_WRITE;
/* Put the data on the bus */
writeBus(data);
/* Raise Req */
setReq(req, 1);
/* Wait for AKN to go high */
/* Need timeout to detect Slave fault */
while(IN_AKN == 0)
{
if(timeout++ == BUS_TIMEOUT)
{
setReq(req, 0);
freeBus();
return BUS_ERROR;
}
}
/* Release bus */
freeBus();
/* Drop Req */
setReq(req, 0);
/* Wait for Slave to release bus */
timeout=0;
while(IN_AKN == 1)
{
if(timeout++ == BUS_TIMEOUT)
return BUS_FAILURE; /* We're totally screwed */
}
return 0;
}
void ILI9325i2c_16::writeCom(byte com) {
clearBit(RS);
writeBus(0x00, com);
}
void ILI9325i2c_16::writeData(byte vh, byte vl) {
setBit(RS);
writeBus(vh, vl);
}
