Ejemplo n.º 1
0
void configTxPipe(uint8_t * adr, uint8_t pltype)
{
  // write TX address
  writeRegCmdBuf(RFM73_CMD_WRITE_REG | RFM73_REG_TX_ADDR, adr, 5);
  // write RX0 address
  writeRegCmdBuf(RFM73_CMD_WRITE_REG | RFM73_REG_RX_ADDR_P0, adr, 5);
  // set static or dynamic payload
  uint8_t tmp;
  tmp = readRegVal(RFM73_REG_DYNPD);
  if (pltype == TX_DPL) // dynamic
    tmp |= 1;
  else
    tmp &= ~(1 << 0);
  writeRegVal(RFM73_CMD_WRITE_REG | RFM73_REG_DYNPD, tmp);
}
Ejemplo n.º 2
0
uint8_t sendPayload(const uint8_t * payload,
		const uint8_t _len,
		const uint8_t toAck)
{
	// turn on the radio
	CE_HIGH;

	// check TX_FIFO
	uint8_t status;
	status = readRegVal(RFM7x_REG_FIFO_STATUS); 
	if (status & RFM7x_FIFO_STATUS_TX_FULL) 
	{
		return 0;
	}

	// send payload
	uint8_t cmd;
	uint8_t len = _len;

	if(toAck == -1){
		cmd = RFM7x_CMD_W_ACK_PAYLOAD;
	}else if (toAck == 0){
		cmd = RFM7x_CMD_W_TX_PAYLOAD_NOACK;
	}else{
		cmd = RFM7x_CMD_WR_TX_PLOAD;
	}
	writeRegCmdBuf(cmd, payload, len);
	return 1;
}
Ejemplo n.º 3
0
// Important! adr has to be 5-bytes length even if MSB bytes are unused
uint8_t configRxPipe(uint8_t pipe_nr,
		uint8_t *adr,
		uint8_t plLen,
		uint8_t en_aa)
{

	uint8_t tmp;
	uint8_t nr = pipe_nr;

	if(plLen > 32 || nr > 5 || en_aa > 1){
		return 0;
	}

	// write address
	if(nr<2)      // full length for rx pipe 0 an 1
		writeRegCmdBuf(RFM7x_CMD_WRITE_REG | (RFM7x_REG_RX_ADDR_P0 + nr), adr, 5);
	else // only LSB for pipes 2..5
		writeRegVal(RFM7x_CMD_WRITE_REG | (RFM7x_REG_RX_ADDR_P0 + nr), adr[0]); 

	// static
	if (plLen) {
		// set payload len
		writeRegVal(RFM7x_CMD_WRITE_REG | (RFM7x_REG_RX_PW_P0 + nr), plLen);
		// set EN_AA bit
		tmp = readRegVal(RFM7x_REG_EN_AA);
		if (en_aa)
			tmp |= 1 << nr;
		else
			tmp &= ~(1 << nr);
		writeRegVal(RFM7x_CMD_WRITE_REG | RFM7x_REG_EN_AA, tmp);
		// clear DPL bit
		tmp = readRegVal(RFM7x_REG_DYNPD);
		tmp &= ~(1 << nr);
		writeRegVal(RFM7x_CMD_WRITE_REG | RFM7x_REG_DYNPD, tmp);        
		// set Enable pipe bit
		enableRxPipe(nr);
	}
	// dynamic
	else 
	{
		// set payload len to default
		writeRegVal(RFM7x_CMD_WRITE_REG | (RFM7x_REG_RX_PW_P0 + nr), 0x20);
		// set EN_AA bit
		tmp = readRegVal(RFM7x_REG_EN_AA);
		tmp |= 1 << nr;
		writeRegVal(RFM7x_CMD_WRITE_REG | RFM7x_REG_EN_AA, tmp);
		// set DPL bit
		tmp = readRegVal(RFM7x_REG_DYNPD);
		tmp |= 1 << nr;
		writeRegVal(RFM7x_CMD_WRITE_REG | RFM7x_REG_DYNPD, tmp);
		// set Enable pipe bit
		enableRxPipe(nr);
	}
	return 1;
}
Ejemplo n.º 4
0
uint8_t RFM70::configRxPipe(uint8_t pipe_nr, uint8_t * adr, uint8_t plLen,
                            uint8_t en_aa) {

    uint8_t tmp;
    uint8_t nr = pipe_nr - 1;

    if (plLen > 32 || nr > 5 || en_aa > 1) {
        return 0;
    }

    // write address
    // full length for rx pipe 0 an 1
    if (nr < 2) {
        writeRegCmdBuf(RFM70_CMD_WRITE_REG | (RFM70_REG_RX_ADDR_P0 + nr), adr,
                       sizeof(adr));
    } else {
        // only LSB for pipes 2..5
        writeRegVal(RFM70_CMD_WRITE_REG | (RFM70_REG_RX_ADDR_P0 + nr), adr[0]); //ODO:check this
    }

    // static
    if (plLen) {
        // set payload len
        writeRegVal(RFM70_CMD_WRITE_REG | (RFM70_REG_RX_PW_P0 + nr), plLen);
        // set EN_AA bit
        tmp = readRegVal(RFM70_REG_EN_AA);
        if (en_aa) {
            tmp |= 1 << nr;
        } else {
            tmp &= ~(1 << nr);
        }
        writeRegVal(RFM70_CMD_WRITE_REG | RFM70_REG_EN_AA, tmp);
        // clear DPL bit
        tmp = readRegVal(RFM70_REG_DYNPD);
        tmp &= ~(1 << nr);
        writeRegVal(RFM70_CMD_WRITE_REG | RFM70_REG_DYNPD, tmp);
        // set Enable pipe bit
        enableRxPipe(nr);
    } else {
        // set payload len to default
        writeRegVal(RFM70_CMD_WRITE_REG | (RFM70_REG_RX_PW_P0 + nr), 0x20);
        // set EN_AA bit
        tmp = readRegVal(RFM70_REG_EN_AA);
        tmp |= 1 << nr;
        writeRegVal(RFM70_CMD_WRITE_REG | RFM70_REG_EN_AA, tmp);
        // set DPL bit
        tmp = readRegVal(RFM70_REG_DYNPD);
        tmp |= 1 << nr;
        writeRegVal(RFM70_CMD_WRITE_REG | RFM70_REG_DYNPD, tmp);
        // set Enable pipe bit
        enableRxPipe(nr);
    }
    return 1;
}