/*
* Setup the local clock events for a CPU.
*/
static int __cpuinit generic_timer_setup(struct clock_event_device *clk)
{
struct clock_event_device **this_cpu_clk;
pr_info("[ca7_timer]%s entry\n", __func__);
generic_timer_calibrate_rate();
write_cntp_ctl(0x0);
clk->name = "generic_timer";
clk->features = CLOCK_EVT_FEAT_ONESHOT;
clk->rating = 350;
clk->set_mode = generic_timer_set_mode;
clk->set_next_event = generic_timer_set_next_event;
clk->irq = timer_ppi;
this_cpu_clk = __this_cpu_ptr(timer_evt);
*this_cpu_clk = clk;
clockevents_config_and_register(clk, generic_timer_rate,
0xf, 0x7fffffff);
enable_percpu_irq(clk->irq, 0);
return 0;
}
void interrupt_nsptimer(int irq, void *pregs, void *pdata )
{
uint32_t ctl;
struct arch_regs *regs = pregs;
uart_print( "=======================================\n\r" );
HVMM_TRACE_ENTER();
/* Disable NS Physical Timer Interrupt */
ctl = read_cntp_ctl();
ctl &= ~(0x1);
write_cntp_ctl(ctl);
/* Trigger another interrupt */
test_start_timer();
/* Test guest context switch */
if ( (regs->cpsr & 0x1F) != 0x1A ) {
/* Not from Hyp, switch the guest context */
context_dump_regs( regs );
context_switchto(sched_policy_determ_next());
}
HVMM_TRACE_EXIT();
uart_print( "=======================================\n\r" );
}
static enum handler_return platform_tick(void *arg)
{
write_cntp_ctl(0);
if (t_callback) {
return t_callback(arg, current_time());
} else {
return INT_NO_RESCHEDULE;
}
}
static void test_operation(void)
{
if (opcode == 0) {
dump_timer_regs();
} else if (opcode == 1) {
write_cntp_tval(op1);
write_cntp_ctl(op2);
}
}
static int generic_timer_set_next_event(unsigned long evt,
struct clock_event_device *unused)
{
write_cntp_tval(evt);
write_cntp_ctl(CNTP_CTL_ENABLE);
save_localtimer_info(evt, 0);
return 0;
}
/*
* generic_timer_ack: checks for a local timer interrupt.
*
* If a local timer interrupt has occurred, acknowledge and return 1.
* Otherwise, return 0.
*/
static int generic_timer_ack(void)
{
unsigned int cntp_ctl;
read_cntp_ctl(cntp_ctl);
if (cntp_ctl & CNTP_CTL_ISTATUS) {
write_cntp_ctl(CNTP_CTL_IMASK);
return 1;
}
printk("WARNING: Generic Timer CNTP_CTL = 0x%x\n", cntp_ctl);
return 0;
}
static int test_ack(void)
{
unsigned int cntp_ctl;
read_cntp_ctl(cntp_ctl);
printk("test_ack: CNTP_CTL = 0x%x\n", cntp_ctl);
if (cntp_ctl & CNTP_CTL_ISTATUS) {
write_cntp_ctl(CNTP_CTL_IMASK);
return 1;
}
return 0;
}
status_t platform_set_oneshot_timer(platform_timer_callback callback, void *arg, lk_time_t interval)
{
uint64_t cntpct_interval = lk_time_to_cntpct(interval);
ASSERT(arg == NULL);
t_callback = callback;
if (cntpct_interval <= INT_MAX)
write_cntp_tval(cntpct_interval);
else
write_cntp_cval(read_cntpct() + cntpct_interval);
write_cntp_ctl(1);
return 0;
}
int spm_wfi_for_sodi_test(void *sodi_data)
{
volatile u32 do_not_change_it;
volatile u32 lo, hi, core_id;
unsigned long flags;
//u32 temp_address;
preempt_disable();
do_not_change_it = 1;
MCDI_Test_Mode = 1;
while(do_not_change_it)
{
/* Mask ARM i bit */
local_irq_save(flags);
core_id = (u32)smp_processor_id();
// set local timer & GPT =========================================
switch (core_id)
{
case 0 :
read_cntp_cval(lo, hi);
hi+=0xffffffff; // very very long
write_cntp_cval(lo, hi);
write_cntp_ctl(0x1); // CNTP_CTL_ENABLE
break;
case 1 :
stop_gpt(GPT4); // disable GPT
break;
default : break;
}
spm_mcdi_wfi();
/* Un-Mask ARM i bit */
local_irq_restore(flags);
}
preempt_enable();
return 0;
}
static void generic_timer_set_mode(enum clock_event_mode mode,
struct clock_event_device *clk)
{
unsigned long ctrl;
switch (mode) {
case CLOCK_EVT_MODE_ONESHOT:
ctrl = CNTP_CTL_ENABLE;
break;
case CLOCK_EVT_MODE_PERIODIC:
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
default:
ctrl = CNTP_CTL_IMASK;
}
write_cntp_ctl(ctrl);
}
static void test_start_timer(void)
{
uint32_t ctl;
uint32_t tval;
uint64_t pct;
HVMM_TRACE_ENTER();
/* every second */
tval = read_cntfrq();
write_cntp_tval(tval);
pct = read_cntpct();
uart_print("cntpct:");
uart_print_hex64(pct);
uart_print("\n\r");
uart_print("cntp_tval:");
uart_print_hex32(tval);
uart_print("\n\r");
/* enable timer */
ctl = read_cntp_ctl();
ctl |= 0x1;
write_cntp_ctl(ctl);
HVMM_TRACE_EXIT();
}
static void __cpuinit generic_timer_calibrate_rate(void)
{
unsigned long count;
u64 waitjiffies;
/*
* If this is the first time round, we need to work out how fast
* the timer ticks
*/
if (generic_timer_rate == 0) {
printk("Calibrating local timer... ");
/* Wait for a tick to start */
waitjiffies = get_jiffies_64() + 1;
while (get_jiffies_64() < waitjiffies)
udelay(10);
/* OK, now the tick has started, let's get the timer going */
waitjiffies += 5;
/* enable, no interrupt or reload */
write_cntp_ctl(CNTP_CTL_ENABLE | CNTP_CTL_IMASK);
/* maximum value */
write_cntp_tval(0xFFFFFFFFU);
while (get_jiffies_64() < waitjiffies)
udelay(10);
read_cntp_tval(count);
generic_timer_rate = (0xFFFFFFFFU - count) * (HZ / 5);
printk("%lu.%02luMHz.\n", generic_timer_rate / 1000000,
(generic_timer_rate / 10000) % 100);
}
}
static void arm_generic_timer_resume_cpu(uint level)
{
/* Always trigger a timer interrupt on each cpu for now */
write_cntp_tval(0);
write_cntp_ctl(1);
}
void platform_stop_timer(void)
{
write_cntp_ctl(0);
}
int spm_wfi_for_mcdi_test(void *mcdi_data)
{
volatile u32 do_not_change_it;
volatile u32 lo, hi, core_id;
unsigned long flags;
preempt_disable();
do_not_change_it = 1;
MCDI_Test_Mode = 1;
while(do_not_change_it)
{
/* Mask ARM i bit */
local_irq_save(flags);
core_id = (u32)smp_processor_id();
// set local timer & GPT =========================================
switch (core_id)
{
case 0 :
#if 0
/*trigger pcm timer*/
spm_write(SPM_POWER_ON_VAL1,(spm_read(SPM_POWER_ON_VAL1)&0xFFFFFFCF)|0x220);
spm_write(SPM_PCM_PWR_IO_EN,0x00800000);
spm_write(SPM_PCM_PWR_IO_EN,0x00000000);
#else
read_cntp_cval(lo, hi);
lo+=26000; // 100 ms, 13MHz
//lo+=5070000; // 390 ms, 13MHz
write_cntp_cval(lo, hi);
write_cntp_ctl(0x1); // CNTP_CTL_ENABLE
//printk("mcdi pdn cnt:%d\n",cpu_power_down_cnt);
#endif
break;
case 1 :
#if 0
//gpt_set_cmp(GPT4, 2470000); // 190ms, 13MHz
//printk("mcdi pdn cnt:%d\n",cpu_power_down_cnt);
gpt_set_cmp(GPT4, 130000); // 10ms, 13MHz
start_gpt(GPT4);
#endif
read_cntp_cval(lo, hi);
lo+=26000; // 100 ms, 13MHz
//lo+=5070000; // 390 ms, 13MHz
write_cntp_cval(lo, hi);
write_cntp_ctl(0x1); // CNTP_CTL_ENABLE
spm_mcdi_before_wfi(core_id);
break;
default : break;
}
spm_mcdi_wfi();
if(core_id==1)
spm_mcdi_after_wfi(core_id);
/* Un-Mask ARM i bit */
local_irq_restore(flags);
}
preempt_enable();
return 0;
}
