static Bool RADEONVIP_fifo_write(GENERIC_BUS_Ptr b, uint32_t address, uint32_t count, uint8_t *buffer)
{
ScrnInfoPtr pScrn = b->pScrn;
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
uint32_t status;
uint32_t i;
RADEONWaitForFifo(pScrn, 2);
OUTREG(VIPH_REG_ADDR, (address & (~0x2000)) | 0x1000);
while(VIP_BUSY == (status = RADEONVIP_fifo_idle(b, 0x0f)));
if(VIP_IDLE != status){
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "cannot write %x to VIPH_REG_ADDR\n", (unsigned int)address);
return FALSE;
}
RADEONWaitForFifo(pScrn, 2);
for (i = 0; i < count; i+=4)
{
OUTREG(VIPH_REG_DATA, *(uint32_t*)(buffer + i));
write_mem_barrier();
while(VIP_BUSY == (status = RADEONVIP_fifo_idle(b, 0x0f)));
if(VIP_IDLE != status)
{
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "cannot write to VIPH_REG_DATA\n");
return FALSE;
}
}
return TRUE;
}
static Bool RADEONVIP_write(GENERIC_BUS_Ptr b, uint32_t address, uint32_t count, uint8_t *buffer)
{
ScrnInfoPtr pScrn = b->pScrn;
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
uint32_t status;
if((count!=4))
{
xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Attempt to access VIP bus with non-stadard transaction length\n");
return FALSE;
}
RADEONWaitForFifo(pScrn, 2);
OUTREG(RADEON_VIPH_REG_ADDR, address & (~0x2000));
while(VIP_BUSY == (status = RADEONVIP_idle(b)));
if(VIP_IDLE != status) return FALSE;
RADEONWaitForFifo(pScrn, 2);
switch(count){
case 4:
OUTREG(RADEON_VIPH_REG_DATA, *(uint32_t *)buffer);
break;
}
write_mem_barrier();
while(VIP_BUSY == (status = RADEONVIP_idle(b)));
if(VIP_IDLE != status) return FALSE;
return TRUE;
}
static void
writeSparse32(int Value, pointer Base, register unsigned long Offset)
{
write_mem_barrier();
*(vuip)((unsigned long)Base + (Offset)) = Value;
return;
}
static void
writeSparse32(int Value, pointer Base, register unsigned long Offset)
{
/* NOTE: this is really using DENSE. */
write_mem_barrier();
*(vuip)((unsigned long)Base + (Offset)) = Value;
return;
}
void
_dense_outb(char val, unsigned long port)
{
if ((port & ~0xffff) == 0) return _outb(val, port);
write_mem_barrier();
*(volatile CARD8 *)port = val;
}
static void
writeSparseJensen8(int Value, pointer Base, register unsigned long Offset)
{
register unsigned int b = Value & 0xffU;
write_mem_barrier();
*(vuip) ((unsigned long)Base + (Offset << SPARSE)) = b * 0x01010101;
}
static void
writeSparseJensen16(int Value, pointer Base, register unsigned long Offset)
{
register unsigned int w = Value & 0xffffU;
write_mem_barrier();
*(vuip)((unsigned long)Base+(Offset<<SPARSE)+(1<<(SPARSE-2))) =
w * 0x00010001;
}
static void
writeSparse16(int Value, pointer Base, register unsigned long Offset)
{
register unsigned long msb;
register unsigned int w = Value & 0xffffU;
write_mem_barrier();
Offset += (unsigned long)Base - DENSE_BASE;
if (Offset >= hae_thresh) {
msb = Offset & hae_mask;
Offset -= msb;
if (msb_set != msb) {
sethae(msb);
msb_set = msb;
}
}
write_mem_barrier();
*(vuip)(SPARSE_BASE + (Offset<<5) + (1<<(5-2))) = w * 0x00010001;
}
static Bool
AlpPrepareSolid(PixmapPtr pPixmap, int alu, Pixel planemask, Pixel fg)
{
ScreenPtr pScreen = pPixmap->drawable.pScreen;
ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen);
CirPtr pCir = CIRPTR(pScrn);
AlpPtr pAlp = ALPPTR(pCir);
int pitch = pCir->pitch;
#ifdef ALP_DEBUG
ErrorF("AlpSetupForSolidFill color=%x alu=%x planemask=%x\n",
fg, alu, planemask);
#endif
WAIT;
SetupForRop(alu);
switch (pCir -> Chipset) {
case PCI_CHIP_GD7548:
/* The GD7548 does not (apparently) support solid filling
directly, it always need an actual source.
We therefore use it as a pattern fill with a solid
pattern */
{
int source = pAlp->monoPattern8x8;
/* source = 8x8 solid mono pattern */
outw(pCir->PIOReg, ((source << 8) & 0xff00) | 0x2C);
outw(pCir->PIOReg, ((source) & 0xff00) | 0x2D);
outw(pCir->PIOReg, ((source >> 8) & 0x3f00) | 0x2E);
/* memset() may not be the fastest */
memset((char *)pCir->FbBase + pAlp->monoPattern8x8, 0xFF, 8);
write_mem_barrier();
break;
}
default:
/* GR33 = 0x04 => does not exist on GD7548 */
outw(pCir->PIOReg, 0x0433);
}
/* GR30 = color expansion, pattern copy */
/* Choses 8bpp / 16bpp color expansion */
outw(pCir->PIOReg, 0xC030 |((pScrn->bitsPerPixel - 8) << 9));
outw(pCir->PIOReg, ((fg << 8) & 0xff00) | 0x01);
outw(pCir->PIOReg, ((fg) & 0xff00) | 0x11);
outw(pCir->PIOReg, ((fg >> 8) & 0xff00) | 0x13);
outw(pCir->PIOReg, 0x15);
/* Set dest pitch */
outw(pCir->PIOReg, ((pitch << 8) & 0xff00) | 0x24);
outw(pCir->PIOReg, ((pitch) & 0x1f00) | 0x25);
return TRUE;
}
static void
writeSparse8(int Value, pointer Base, register unsigned long Offset)
{
register unsigned long msb;
register unsigned int b = Value & 0xffU;
write_mem_barrier();
Offset += (unsigned long)Base - (unsigned long)memBase;
if (Offset >= (hae_thresh)) {
msb = Offset & hae_mask;
Offset -= msb;
if (msb_set != msb) {
#ifndef __NetBSD__
sethae(msb);
#endif
msb_set = msb;
}
}
*(vuip) ((unsigned long)memSBase + (Offset << 5)) = b * 0x01010101;
}
void
writeDense32(int Value, pointer Base, register unsigned long Offset)
{
write_mem_barrier();
*(volatile CARD32 *)((unsigned long)Base+(Offset)) = Value;
}
static void
writeSparseJensen32(int Value, pointer Base, register unsigned long Offset)
{
write_mem_barrier();
*(vuip)((unsigned long)Base+(Offset<<SPARSE)+(3<<(SPARSE-2))) = Value;
}
static Bool RADEONVIP_fifo_read(GENERIC_BUS_Ptr b, uint32_t address, uint32_t count, uint8_t *buffer)
{
ScrnInfoPtr pScrn = b->pScrn;
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
uint32_t status,tmp;
if(count!=1)
{
xf86DrvMsg(pScrn->scrnIndex,X_ERROR,"Attempt to access VIP bus with non-stadard transaction length\n");
return FALSE;
}
RADEONWaitForFifo(pScrn, 2);
OUTREG(VIPH_REG_ADDR, address | 0x3000);
write_mem_barrier();
while(VIP_BUSY == (status = RADEONVIP_fifo_idle(b, 0xff)));
if(VIP_IDLE != status) return FALSE;
/*
disable VIPH_REGR_DIS to enable VIP cycle.
The LSB of VIPH_TIMEOUT_STAT are set to 0
because 1 would have acknowledged various VIP
interrupts unexpectedly
*/
RADEONWaitForIdleMMIO(pScrn);
OUTREG(VIPH_TIMEOUT_STAT, INREG(VIPH_TIMEOUT_STAT) & (0xffffff00 & ~VIPH_TIMEOUT_STAT__VIPH_REGR_DIS) );
write_mem_barrier();
/*
the value returned here is garbage. The read merely initiates
a register cycle
*/
RADEONWaitForIdleMMIO(pScrn);
INREG(VIPH_REG_DATA);
while(VIP_BUSY == (status = RADEONVIP_fifo_idle(b, 0xff)));
if(VIP_IDLE != status) return FALSE;
/*
set VIPH_REGR_DIS so that the read won't take too long.
*/
RADEONWaitForIdleMMIO(pScrn);
tmp=INREG(VIPH_TIMEOUT_STAT);
OUTREG(VIPH_TIMEOUT_STAT, (tmp & 0xffffff00) | VIPH_TIMEOUT_STAT__VIPH_REGR_DIS);
write_mem_barrier();
RADEONWaitForIdleMMIO(pScrn);
switch(count){
case 1:
*buffer=(uint8_t)(INREG(VIPH_REG_DATA) & 0xff);
break;
case 2:
*(uint16_t *)buffer=(uint16_t) (INREG(VIPH_REG_DATA) & 0xffff);
break;
case 4:
*(uint32_t *)buffer=(uint32_t) ( INREG(VIPH_REG_DATA) & 0xffffffff);
break;
}
while(VIP_BUSY == (status = RADEONVIP_fifo_idle(b, 0xff)));
if(VIP_IDLE != status) return FALSE;
/*
so that reading VIPH_REG_DATA would not trigger unnecessary vip cycles.
*/
OUTREG(VIPH_TIMEOUT_STAT, (INREG(VIPH_TIMEOUT_STAT) & 0xffffff00) | VIPH_TIMEOUT_STAT__VIPH_REGR_DIS);
write_mem_barrier();
return TRUE;
}
