static void
atrtc_start(void)
{
writertc(RTC_STATUSA, rtc_statusa);
writertc(RTC_STATUSB, RTCSB_24HR);
}
static int
atrtc_settime(device_t dev __unused, struct timespec *ts)
{
struct clocktime ct;
clock_ts_to_ct(ts, &ct);
/* Disable RTC updates and interrupts. */
writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR);
writertc(RTC_SEC, bin2bcd(ct.sec)); /* Write back Seconds */
writertc(RTC_MIN, bin2bcd(ct.min)); /* Write back Minutes */
writertc(RTC_HRS, bin2bcd(ct.hour)); /* Write back Hours */
writertc(RTC_WDAY, ct.dow + 1); /* Write back Weekday */
writertc(RTC_DAY, bin2bcd(ct.day)); /* Write back Day */
writertc(RTC_MONTH, bin2bcd(ct.mon)); /* Write back Month */
writertc(RTC_YEAR, bin2bcd(ct.year % 100)); /* Write back Year */
#ifdef USE_RTC_CENTURY
writertc(RTC_CENTURY, bin2bcd(ct.year / 100)); /* ... and Century */
#endif
/* Reenable RTC updates and interrupts. */
writertc(RTC_STATUSB, rtc_statusb);
rtcin(RTC_INTR);
return (0);
}
void
atrtc_restore(void)
{
/* Restore all of the RTC's "status" (actually, control) registers. */
rtcin(RTC_STATUSA); /* dummy to get rtc_reg set */
writertc(RTC_STATUSB, RTCSB_24HR);
writertc(RTC_STATUSA, rtc_statusa);
writertc(RTC_STATUSB, rtc_statusb);
rtcin(RTC_INTR);
}
static void
atrtc_rate(unsigned rate)
{
rtc_statusa = RTCSA_DIVIDER | rate;
writertc(RTC_STATUSA, rtc_statusa);
}
static void
atrtc_disable_intr(void)
{
rtc_statusb &= ~RTCSB_PINTR;
writertc(RTC_STATUSB, rtc_statusb);
rtcin(RTC_INTR);
}
void
atrtc_enable_intr(void)
{
rtc_statusb |= RTCSB_PINTR;
writertc(RTC_STATUSB, rtc_statusb);
rtcin(RTC_INTR);
}
static uint64_t
malta_cpu_freq(void)
{
uint64_t platform_counter_freq = 0;
#if defined(TICK_USE_YAMON_FREQ)
/*
* If we are running on a board which uses YAMON firmware,
* then query CPU pipeline clock from the syscon object.
* If unsuccessful, use hard-coded default.
*/
platform_counter_freq = yamon_getcpufreq();
#elif defined(TICK_USE_MALTA_RTC)
/*
* If we are running on a board with the MC146818 RTC,
* use it to determine CPU pipeline clock frequency.
*/
u_int64_t counterval[2];
/* Set RTC to binary mode. */
writertc(RTC_STATUSB, (rtcin(RTC_STATUSB) | RTCSB_BCD));
/* Busy-wait for falling edge of RTC update. */
while (((rtcin(RTC_STATUSA) & RTCSA_TUP) == 0))
;
while (((rtcin(RTC_STATUSA)& RTCSA_TUP) != 0))
;
counterval[0] = mips_rd_count();
/* Busy-wait for falling edge of RTC update. */
while (((rtcin(RTC_STATUSA) & RTCSA_TUP) == 0))
;
while (((rtcin(RTC_STATUSA)& RTCSA_TUP) != 0))
;
counterval[1] = mips_rd_count();
platform_counter_freq = counterval[1] - counterval[0];
#endif
if (platform_counter_freq == 0)
platform_counter_freq = MIPS_DEFAULT_HZ;
return (platform_counter_freq);
}
void
platform_start(__register_t a0, __register_t a1, __register_t a2,
__register_t a3)
{
vm_offset_t kernend;
uint64_t platform_counter_freq;
int argc = a0;
char **argv = (char **)a1;
char **envp = (char **)a2;
unsigned int memsize = a3;
int i;
/* clear the BSS and SBSS segments */
kernend = round_page((vm_offset_t)&end);
memset(&edata, 0, kernend - (vm_offset_t)(&edata));
cninit();
printf("entry: platform_start()\n");
bootverbose = 1;
if (bootverbose) {
printf("cmd line: ");
for (i = 0; i < argc; i++)
printf("%s ", argv[i]);
printf("\n");
printf("envp:\n");
for (i = 0; envp[i]; i += 2)
printf("\t%s = %s\n", envp[i], envp[i+1]);
printf("memsize = %08x\n", memsize);
}
realmem = btoc(memsize);
mips_init();
do {
#if defined(TICK_USE_YAMON_FREQ)
/*
* If we are running on a board which uses YAMON firmware,
* then query CPU pipeline clock from the syscon object.
* If unsuccessful, use hard-coded default.
*/
platform_counter_freq = yamon_getcpufreq();
if (platform_counter_freq == 0)
platform_counter_freq = MIPS_DEFAULT_HZ;
#elif defined(TICK_USE_MALTA_RTC)
/*
* If we are running on a board with the MC146818 RTC,
* use it to determine CPU pipeline clock frequency.
*/
u_int64_t counterval[2];
/* Set RTC to binary mode. */
writertc(RTC_STATUSB, (rtcin(RTC_STATUSB) | RTCSB_BCD));
/* Busy-wait for falling edge of RTC update. */
while (((rtcin(RTC_STATUSA) & RTCSA_TUP) == 0))
;
while (((rtcin(RTC_STATUSA)& RTCSA_TUP) != 0))
;
counterval[0] = mips_rd_count();
/* Busy-wait for falling edge of RTC update. */
while (((rtcin(RTC_STATUSA) & RTCSA_TUP) == 0))
;
while (((rtcin(RTC_STATUSA)& RTCSA_TUP) != 0))
;
counterval[1] = mips_rd_count();
platform_counter_freq = counterval[1] - counterval[0];
#endif
} while(0);
mips_timer_init_params(platform_counter_freq, 0);
}
