void beacon_sequence()
{
static int beacon_seq_state = 0;
switch ( beacon_seq_state )
{
case 0:
// send data if enough time passed since last send
if ( gettime() - ble_txtime > BLE_INTERVAL )
{
ble_send = 1;
oldchan = rf_chan;
send_beacon();
beacon_seq_state++;
}
break;
case 1:
// wait for data to finish transmitting
if( (xn_readreg(0x17)&B00010000) )
{
xn_writereg( 0 , XN_TO_RX );
xn_writereg(0x25, rfchannel[oldchan]);
beacon_seq_state++;
goto next;
}
else
{// if it takes too long we get rid of it
if ( gettime() - ble_txtime > BLE_TX_TIMEOUT )
{
xn_command( FLUSH_TX);
xn_writereg( 0 , XN_TO_RX );
beacon_seq_state++;
ble_send = 0;
}
}
break;
case 2:
next:
// restore radio settings to protocol compatible
// mainly channel here if bind
ble_send = 0;
if ( rxmode == 0 )
{
xn_writereg(0x25, 0 ); // Set channel frequency , bind
}
beacon_seq_state++;
break;
default:
beacon_seq_state = 0;
break;
}
}
void rx_init()
{
writeregs( bbcal , sizeof(bbcal) );
writeregs( rfcal , sizeof(rfcal) );
writeregs( demodcal , sizeof(demodcal) );
int rxaddress[5] = {0xCC,0xCC,0xCC,0xCC,0xCC};
xn_writerxaddress( rxaddress);
xn_writetxaddress( rxaddress);
xn_writereg( EN_AA , 0 ); // aa disabled
xn_writereg( EN_RXADDR , 1 ); // pipe 0 only
// xn_writereg( RF_SETUP , B00000001); // lna high current on ( better performance )
xn_writereg( RF_SETUP , B00000111);
xn_writereg( RX_PW_P0 , PAYLOAD_LENGHT ); // payload size
xn_writereg( SETUP_RETR , 0 ); // no retransmissions ( redundant?)
xn_writereg( SETUP_AW , 3 ); // address size (5 bits)
xn_command( FLUSH_RX);
xn_writereg( RF_CH , 2 ); // bind channel
xn_writereg( 0 , B00001111 ); // power up, crc enabled
}
void rx_init()
{
uint8_t bbcal[6] = { 0x3f , 0x4c , 0x84 , 0x6F , 0x9c , 0x20 };
writeregs( bbcal , sizeof(bbcal) );
uint8_t rfcal[8] = { 0x3e , 0xc9 , 0x9a , 0x80 , 0x61 , 0xbb , 0xab , 0x9c };
writeregs( rfcal , sizeof(rfcal) );
uint8_t demodcal[6] = { 0x39 , 0x0b , 0xdf , 0xc4 , 0xa7 , 0x03};
writeregs( demodcal , sizeof(demodcal) );
int rxaddress[5] = { 0 , 0 , 0 , 0 , 0 };
xn_writerxaddress( rxaddress);
xn_writereg( EN_AA , 0 ); // aa disabled
xn_writereg( EN_RXADDR , 1 ); // pipe 0 only
xn_writereg( RF_SETUP , B00000001); // lna high current on ( better performance )
xn_writereg( RX_PW_P0 , 15 ); // payload size
xn_writereg( SETUP_RETR , 0 ); // no retransmissions ( redundant?)
xn_writereg( SETUP_AW , 3 ); // address size (5 bits)
xn_command( FLUSH_RX);
xn_writereg( RF_CH , 0 ); // bind on channel 0
xn_writereg( 0 , B00001111 ); // power up, crc enabled
#ifdef RADIO_CHECK
void check_radio(void);
check_radio();
#endif
}
void send_beacon()
{
// Channel hopping
ch++;
if (ch>2 )
{
ch = 0;
}
// sending on channel 37 only to use whitening array
if (ONE_CHANNEL) ch = 0;
xn_writereg(RF_CH, chRf[ch]);
uint8_t L=0;
#ifdef USE_IBEACON
L=0;
// ibeacon packet structure
buf[L++] = B00100010; //PDU type, given address is random; 0x42 for Android and 0x40 for iPhone
buf[L++] = 36; // length of payload
buf[L++] = MY_MAC_0;
buf[L++] = MY_MAC_1;
buf[L++] = MY_MAC_2;
buf[L++] = MY_MAC_3;
buf[L++] = MY_MAC_4;
buf[L++] = MY_MAC_5;
// packet data unit
buf[L++] = 2; //flags (LE-only, limited discovery mode)
buf[L++] = 0x01;
buf[L++] = 0x06;
buf[L++] = 0x1A; // length of the name, including type byte
buf[L++] = 0xff;
buf[L++] = 0x4c;
buf[L++] = 0x00;
buf[L++] = 0x02;
buf[L++] = 0x15;
buf[L++] = 0x58;
buf[L++] = 0x5c;
buf[L++] = 0xde;
buf[L++] = 0x93;
buf[L++] = 0x1b;
buf[L++] = 0x01;
buf[L++] = 0x42;
buf[L++] = 0xcc;
buf[L++] = 0x9a;
buf[L++] = 0x13;
buf[L++] = 0x25;
buf[L++] = 0x00;
buf[L++] = 0x9b;
buf[L++] = 0xed;
buf[L++] = 0xc6;
buf[L++] = 0xe5;
buf[L++] = 0x00;
buf[L++] = 0x00;
buf[L++] = 0x00;
buf[L++] = 0x00;
buf[L++] = 0xCA; // tx power
#else
extern float vbattfilt;
int vbatt = vbattfilt *1000.0f;
unsigned int time = gettime();
time = time>>20; // divide by 1024*1024, no time for accuracy here
time = time * 10;
L=0;
buf[L++] = B00100010; //PDU type, given address is random; 0x42 for Android and 0x40 for iPhone
//buf[L++] = 0x42; //PDU type, given address is random; 0x42 for Android and 0x40 for iPhone
// max len 27 with 5 byte address = 37 total payload bytes
buf[L++] = 10+ 21; // length of payload
buf[L++] = MY_MAC_0;
buf[L++] = MY_MAC_1;
buf[L++] = MY_MAC_2;
buf[L++] = MY_MAC_3;
buf[L++] = MY_MAC_4;
buf[L++] = MY_MAC_5;
// packet data unit
buf[L++] = 2; //flags lenght(LE-only, limited discovery mode)
buf[L++] = 0x01; // compulsory flags
buf[L++] = 0x06; // flag value
buf[L++] = 0x03; // Length of next block
buf[L++] = 0x03; // Param: Service List
buf[L++] = 0xAA; // Eddystone ID - 16 bit 0xFEAA
buf[L++] = 0xFE; // Eddystone ID
buf[L++] = 0x11; // Length of next block
buf[L++] = 0x16; // Service Data
buf[L++] = 0xAA; // Eddystone ID
buf[L++] = 0xFE; // Eddystone ID
buf[L++] = 0x20; // TLM flag
buf[L++] = 0x00; // TLM version
buf[L++] = vbatt>>8; // Battery voltage
buf[L++] = vbatt; // Battery voltage
buf[L++] = 0x80; // temperature 8.8 fixed point
buf[L++] = 0x00; // temperature 8.8 fixed point
buf[L++] = 0x00; // advertisment count 0
buf[L++] = 0x00; // advertisment count 1
buf[L++] = packetpersecond>>8&0xff; // advertisment count 2
buf[L++] = packetpersecond&0xff; // advertisment count 3
buf[L++] = time>>24; // powerup time 0
buf[L++] = time>>16; // powerup time 1
buf[L++] = time>>8; // powerup time 2
buf[L++] = time; // powerup time 3 in seconds times 10.
#endif
L=L+3; //crc
btLePacketEncode(buf, L, ch );
// undo xn297 data whitening
for (uint8_t i = 0; i < L; ++i)
{
buf[i] = buf[i] ^ xn297_scramble_rev[i+ XN297_ADDRESS_SIZE_BLE] ;
}
for( int i = 0 ; i < L ; i++) buffint[i] = buf[i];
xn_command( FLUSH_TX);
xn_writereg( 0 , XN_TO_TX );
payloadsize = L;
xn_writepayload( buffint , L );
ble_txtime = gettime();
return;
}
void rx_init()
{
// always on (CH_ON) channel set 1
aux[AUXNUMBER - 2] = 1;
// always off (CH_OFF) channel set 0
aux[AUXNUMBER - 1] = 0;
#ifdef AUX1_START_ON
aux[CH_AUX1] = 1;
#endif
#ifdef RADIO_XN297L
#define XN_TO_RX B10001111
#define XN_TO_TX B10000010
#define XN_POWER B00111111
#endif
#ifdef RADIO_XN297
static uint8_t bbcal[6] = { 0x3f , 0x4c , 0x84 , 0x6F , 0x9c , 0x20 };
writeregs( bbcal , sizeof(bbcal) );
// new values
static uint8_t rfcal[8] = { 0x3e , 0xc9 , 0x9a , 0xA0 , 0x61 , 0xbb , 0xab , 0x9c };
writeregs( rfcal , sizeof(rfcal) );
static uint8_t demodcal[6] = { 0x39 , 0x0b , 0xdf , 0xc4 , 0xa7 , 0x03};
writeregs( demodcal , sizeof(demodcal) );
#define XN_TO_RX B00001111
#define XN_TO_TX B00000010
#define XN_POWER B00000111
#endif
bleinit();
delay(100);
int rxaddress[5] = { 0 , 0 , 0 , 0 , 0 };
xn_writerxaddress( rxaddress);
xn_writereg( EN_AA , 0 ); // aa disabled
xn_writereg( EN_RXADDR , 1 ); // pipe 0 only
xn_writereg( RF_SETUP , XN_POWER); // lna high current on ( better performance )
xn_writereg( RX_PW_P0 , 15 ); // payload size
xn_writereg( SETUP_RETR , 0 ); // no retransmissions ( redundant?)
xn_writereg( SETUP_AW , 3 ); // address size (5 bits)
xn_command( FLUSH_RX);
xn_writereg( RF_CH , 0 ); // bind on channel 0
// set above
// xn_writereg( 29 , 32); // feture reg , CE mode (software controlled)
#ifdef RADIO_XN297L
xn_writereg( 0x1d, B00111000 ); // 64 bit payload , software ce
spi_cson();
spi_sendbyte( 0xFD); // internal CE high command
spi_sendbyte( 0); // required for above
spi_csoff();
#endif
#ifdef RADIO_XN297
xn_writereg( 0x1d, B00011000 ); // 64 bit payload , software ce
#endif
xn_writereg( 0 , XN_TO_RX ); // power up, crc enabled, rx mode
#ifdef RADIO_CHECK
void check_radio(void);
check_radio();
#endif
}
void rx_init()
{
// always on (CH_ON) channel set 1
aux[AUXNUMBER - 2] = 1;
// always off (CH_OFF) channel set 0
aux[AUXNUMBER - 1] = 0;
#ifdef AUX1_START_ON
aux[CH_AUX1] = 1;
#endif
#ifdef AUX4_START_ON
aux[CH_AUX4] = 1;
#endif
#ifdef RADIO_XN297L
#define XN_TO_RX B10001111
#define XN_TO_TX B10000010
#define XN_POWER B00111111
#endif
#ifdef RADIO_XN297
static uint8_t bbcal[6] = { 0x3f , 0x4c , 0x84 , 0x6F , 0x9c , 0x20 };
writeregs( bbcal , sizeof(bbcal) );
// new values
static uint8_t rfcal[8] = { 0x3e , 0xc9 , 0x9a , 0xA0 , 0x61 , 0xbb , 0xab , 0x9c };
writeregs( rfcal , sizeof(rfcal) );
static uint8_t demodcal[6] = { 0x39 , 0x0b , 0xdf , 0xc4 , 0xa7 , 0x03};
//static uint8_t demodcal[6] = { 0x39 , 0x0b , 0xdf , 0xc4 , B00100111 , B00000000};
writeregs( demodcal , sizeof(demodcal) );
#define XN_TO_RX B00001111
#define XN_TO_TX B00000010
//#define XN_POWER B00000111 // disabled by silverAG for SilverVISE - value is added from config.h
// SilverVISE - start:
#ifdef TX_POWER_GENERAL
// use value from config.h
#define XN_POWER TX_POWER_GENERAL
#else
#define XN_POWER B00000111
#endif
// SilverVISE - end
#endif
bleinit();
delay(100);
int rxaddress[5] = { 0 , 0 , 0 , 0 , 0 };
xn_writerxaddress( rxaddress);
xn_writereg( EN_AA , 0 ); // aa disabled
xn_writereg( EN_RXADDR , 1 ); // pipe 0 only
xn_writereg( RF_SETUP , XN_POWER); // lna high current on ( better performance )
xn_writereg( RX_PW_P0 , 15 ); // payload size
xn_writereg( SETUP_RETR , 0 ); // no retransmissions ( redundant?)
xn_writereg( SETUP_AW , 3 ); // address size (5 bits)
xn_command( FLUSH_RX);
xn_writereg( RF_CH , 0 ); // bind on channel 0
#ifdef RADIO_XN297L
xn_writereg( 0x1d, B00111000 ); // 64 bit payload , software ce
spi_cson();
spi_sendbyte( 0xFD); // internal CE high command
spi_sendbyte( 0); // required for above
spi_csoff();
#endif
#ifdef RADIO_XN297
xn_writereg( 0x1d, B00011000 ); // 64 bit payload , software ce
#endif
xn_writereg( 0 , XN_TO_RX ); // power up, crc enabled, rx mode
#ifdef RADIO_CHECK
int rxcheck = xn_readreg( 0x0f); // rx address pipe 5
// should be 0xc6
extern void failloop( int);
if ( rxcheck != 0xc6) failloop(3);
#endif
}
