int usleep(uint32_t usecs) {
uint64_t start = system_time(0);
while (system_time(start) < usecs) {
yield_if_possible();
}
return 0;
}
int usart_putc(char c, void *env) {
/* Wait until transmit FIFO not full*/
while (UART0_FR_R & UART_FR_TXFF) {
yield_if_possible();
}
UART0_DR_R = c;
return 1;
}
char usart_getc(void *env, int *error) {
if (error != NULL) {
*error = 0;
}
/* Wait for data */
while (UART0_FR_R & UART_FR_RXFE) {
yield_if_possible();
}
return UART0_DR_R & UART_DR_DATA_M;
}
char usart_getc(void *env, int *error) {
if (!usart_ready) {
if (error != NULL) {
*error = -1;
}
return 0;
}
if (error != NULL) {
*error = 0;
}
static uint32_t read = 0;
uint16_t dma_read = USART_DMA_MSIZE - (uint16_t) *DMA2_NDTR_S(2);
uint8_t wrapped = *DMA2_LISR & DMA_LISR_TCIF2;
char *usart_buf = usart_rx_buf;
/* Waiting... */
while (!wrapped && dma_read == read) {
yield_if_possible();
dma_read = USART_DMA_MSIZE - (uint16_t) *DMA2_NDTR_S(2);
wrapped = *DMA2_LISR & DMA_LISR_TCIF2;
}
/* DMA has not wrapped around and is ahead of us */
if (!wrapped && dma_read >= read) {
read += 1;
return *(usart_buf + (read-1));
}
/* The DMA has not wrapped around, yet is somehow behind us, start over */
else if (!wrapped && dma_read < read) {
read = 1;
return *usart_buf;
}
/* The DMA has wrapped around, but hasn't caught up to us yet */
else if (wrapped && dma_read < read) {
read += 1;
return *(usart_buf + (read-1));
}
/* The DMA has wrapped around, and has already caught up to us, start over */
else {
/* Clear completion flag */
*DMA2_LIFCR |= DMA_LIFCR_CTCIF2;
read = 1;
return *usart_buf;
}
}
void deq_test(int argc, char **argv) {
if (argc != 1) {
printf("Usage: %s\r\n", argv[0]);
return;
}
message_t *m1 = malloc(sizeof(message_t));
if (m1 == NULL) {
printf("Unable to malloc m1\r\n");
return;
}
m1->m = "Message 1";
message_t *m2 = malloc(sizeof(message_t));
if (m1 == NULL) {
printf("Unable to malloc m1\r\n");
return;
}
m2->m = "Message 2";
message_t *m3 = malloc(sizeof(message_t));
if (m1 == NULL) {
printf("Unable to malloc m1\r\n");
return;
}
m3->m = "Message 3";
sdeq_add(&deque, m1);
sdeq_add(&deque, m2);
sdeq_add(&deque, m3);
new_task(&t1, 1, 40);
new_task(&t2, 1, 100);
yield_if_possible();
/* Make sure other tasks are done */
usleep(1000000);
list_t *l = __sdeq_pop(&deque);
while(l) {
message_t *m = container_of(l, message_t, _list);
printf("deq_test got: %s\r\n", m->m);
free(m);
l = __sdeq_pop(&deque);
}
}
static char usbdev_resource_read(void *env, int *error) {
if (!usb_ready) {
if (error != NULL) {
*error = -1;
}
return 0;
}
if (error != NULL) {
*error = 0;
}
while (ring_buf_empty(&ep_rx.rx)) {
yield_if_possible();
}
char c = (char) ep_rx.rx.buf[ep_rx.rx.start];
ep_rx.rx.start = (ep_rx.rx.start + 1) % ep_rx.rx.len;
return c;
}
int usart_puts(char *s, void *env) {
if (!usart_ready) {
return -1;
}
int total = 0;
while (*s) {
char *buf = usart_tx_buf;
uint16_t count = 0;
/* Wait for DMA to be ready */
while (*DMA2_CR_S(7) & DMA_SxCR_EN) {
yield_if_possible();
}
if (*DMA2_HISR & DMA_HISR_TCIF7) {
/* Clear transfer complete flag */
*DMA2_HIFCR |= DMA_HIFCR_CTCIF7;
}
/* Copy into buffer */
while (*s && count < USART_DMA_MSIZE) {
count += 1;
*buf++ = *s++;
}
/* Number of bytes to write */
*DMA2_NDTR_S(7) = (uint16_t) count;
/* Enable DMA */
*DMA2_CR_S(7) |= DMA_SxCR_EN;
total += count;
}
return total;
}
int usart_putc(char c, void *env) {
if (!usart_ready) {
return -1;
}
/* Wait for DMA to be ready */
while (*DMA2_CR_S(7) & DMA_SxCR_EN) {
yield_if_possible();
}
if (*DMA2_HISR & DMA_HISR_TCIF7) {
/* Clear transfer complete flag */
*DMA2_HIFCR |= DMA_HIFCR_CTCIF7;
}
*usart_tx_buf = c;
/* 1 byte to write */
*DMA2_NDTR_S(7) = 1;
/* Enable DMA */
*DMA2_CR_S(7) |= DMA_SxCR_EN;
return 1;
}
/* Returns bytes written, negative on error */
int usbdev_write(struct endpoint *ep, uint8_t *packet, int size) {
if (ep == NULL) {
DEBUG_PRINT("Warning: Invalid endpoint in usbdev_write. ");
return -1;
}
if (ep->num != 0 && !usb_ready) {
return -1;
}
if (ep->tx.buf == NULL) {
DEBUG_PRINT("Warning: Endpoint has no tx buffer in usbdev_write. ");
return -1;
}
/* Wait until current buffer is empty */
while (!ring_buf_empty(&ep->tx)) {
yield_if_possible();
}
int filled_buffer = 0;
int written = 0;
/* Copy to ring buffer */
while (size > 0 && !ring_buf_full(&ep->tx)) {
ep->tx.buf[ep->tx.end] = *packet++;
size--;
written++;
ep->tx.end = (ep->tx.end + 1) % ep->tx.len;
}
if (ring_buf_full(&ep->tx)) {
filled_buffer = 1;
}
uint8_t packets = written % ep->mpsize ? written/ep->mpsize + 1 : written/ep->mpsize;
if (!packets) {
packets = 1;
}
int count = 500;
/* Setup endpoint for transmit */
if (ep->num == 0) {
/* Wait for ep to disable */
while (*USB_FS_DIEPCTL0 & USB_FS_DIEPCTL0_EPENA && count > 0) {
count--;
}
/* Abort timed out transfer */
if (count <= 0) {
ep->request_disable = 1;
*USB_FS_DIEPCTL0 |= USB_FS_DIEPCTL0_SNAK;
*USB_FS_DIEPMSK |= USB_FS_DIEPMSK_INEPNEM | USB_FS_DIEPMSK_EPDM;
/* Wait for endpoint to disable */
while(ep->request_disable);
*USB_FS_DIEPMSK &= ~(USB_FS_DIEPMSK_INEPNEM | USB_FS_DIEPMSK_EPDM);
}
*USB_FS_DIEPTSIZ0 = USB_FS_DIEPTSIZ0_PKTCNT(packets) | USB_FS_DIEPTSIZ0_XFRSIZ(written);
*USB_FS_DIEPCTL0 |= USB_FS_DIEPCTL0_CNAK | USB_FS_DIEPCTL0_EPENA;
}
else {
/* Wait for ep to disable */
while (*USB_FS_DIEPCTL(ep->num) & USB_FS_DIEPCTLx_EPENA && count > 0) {
count--;
}
/* Abort timed out transfer */
if (count <= 0) {
ep->request_disable = 1;
*USB_FS_DIEPCTL(ep->num) |= USB_FS_DIEPCTLx_SNAK;
*USB_FS_DIEPMSK |= USB_FS_DIEPMSK_INEPNEM | USB_FS_DIEPMSK_EPDM;
/* Wait for endpoint to disable */
while(ep->request_disable);
*USB_FS_DIEPMSK &= ~(USB_FS_DIEPMSK_INEPNEM | USB_FS_DIEPMSK_EPDM);
}
*USB_FS_DIEPTSIZ(ep->num) = USB_FS_DIEPTSIZx_PKTCNT(packets) | USB_FS_DIEPTSIZx_XFRSIZ(written);
*USB_FS_DIEPCTL(ep->num) |= USB_FS_DIEPCTLx_CNAK | USB_FS_DIEPCTLx_EPENA;
}
/* Enable TX FIFO empty interrupt */
*USB_FS_DIEPEMPMSK |= (1 << ep->num);
/* Filled buffer, call recursively until packet finishes */
if (filled_buffer && size) {
int ret = usbdev_write(ep, packet, size);
if (ret >= 0) {
written += ret;
}
else {
written = ret;
}
}
return written;
}
