void ParityAggrLit::accept(::Printer *v)
{
Printer *printer = v->output()->printer<Printer>();
printer->begin(head(), sign_, even_==fixed_, set_);
foreach(CondLit &lit, conds_) lit.accept(printer);
printer->end();
}
void JunctionAggrLit::accept(::Printer *v)
{
Printer *printer = v->output()->printer<Printer>();
printer->begin(head());
foreach(CondLit &lit, conds_) lit.accept(printer);
printer->end();
}
void MinMaxAggrLit::_accept(::Printer *v)
{
Printer<MinMaxAggrLit, T> *printer = v->output()->printer<Printer<MinMaxAggrLit, T> >();
printer->begin(AggrCond::Printer::State(aggrUid(), domain_.lastId()), head(), sign_, complete(), set_);
if(lower()) { printer->lower(valLower_, lowerEq_); }
if(upper()) { printer->upper(valUpper_, upperEq_); }
printer->end();
}
bool Display::grounded(Grounder *g)
{
Printer *printer = g->output()->printer<Printer>();
printer->begin(static_cast<DisplayHeadLit&>(*head_).val(g), type_);
foreach(Lit &lit, body_)
{
lit.grounded(g);
if(!lit.fact() || lit.forcePrint()) { lit.accept(printer); }
}
void SumAggrLit::accept(::Printer *v)
{
Printer *printer = v->output()->printer<Printer>();
printer->begin(head(), sign_, set());
if(lower_.get() || assign_) printer->lower(lowerBound_);
if(upper_.get() || assign_) printer->upper(upperBound_);
foreach(CondLit &lit, conds_) lit.accept(printer);
printer->end();
}
bool External::grounded(Grounder *g)
{
head_->grounded(g);
if (head_->fact()) { return true; }
addDomain(g);
Printer *printer = g->output()->printer<Printer>();
printer->begin();
if(head_.get()) { head_->accept(printer); }
printer->endHead();
foreach(Lit &lit, body_)
{
lit.grounded(g);
if(!lit.fact()) { lit.accept(printer); }
else if(lit.forcePrint()) { lit.accept(printer); }
}